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@@ -61,6 +61,7 @@ struct rk_priv_data {
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struct clk *mac_clk_tx;
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struct clk *clk_mac_ref;
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struct clk *clk_mac_refout;
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+ struct clk *clk_mac_speed;
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struct clk *aclk_mac;
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struct clk *pclk_mac;
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struct clk *clk_phy;
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@@ -83,6 +84,64 @@ struct rk_priv_data {
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(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
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((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
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+#define PX30_GRF_GMAC_CON1 0x0904
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+
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+/* PX30_GRF_GMAC_CON1 */
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+#define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
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+ GRF_BIT(6))
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+#define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
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+#define PX30_GMAC_SPEED_100M GRF_BIT(2)
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+
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+static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
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+{
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+ struct device *dev = &bsp_priv->pdev->dev;
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+
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+ if (IS_ERR(bsp_priv->grf)) {
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+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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+ return;
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+ }
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+
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+ regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
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+ PX30_GMAC_PHY_INTF_SEL_RMII);
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+}
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+
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+static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
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+{
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+ struct device *dev = &bsp_priv->pdev->dev;
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+ int ret;
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+
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+ if (IS_ERR(bsp_priv->clk_mac_speed)) {
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+ dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
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+ return;
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+ }
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+
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+ if (speed == 10) {
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+ regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
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+ PX30_GMAC_SPEED_10M);
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+
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+ ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000);
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+ if (ret)
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+ dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
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+ __func__, ret);
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+ } else if (speed == 100) {
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+ regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
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+ PX30_GMAC_SPEED_100M);
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+
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+ ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000);
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+ if (ret)
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+ dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
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+ __func__, ret);
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+
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+ } else {
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+ dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
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+ }
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+}
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+
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+static const struct rk_gmac_ops px30_ops = {
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+ .set_to_rmii = px30_set_to_rmii,
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+ .set_rmii_speed = px30_set_rmii_speed,
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+};
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+
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#define RK3128_GRF_MAC_CON0 0x0168
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#define RK3128_GRF_MAC_CON1 0x016c
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@@ -1042,6 +1101,10 @@ static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
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}
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}
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+ bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
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+ if (IS_ERR(bsp_priv->clk_mac_speed))
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+ dev_err(dev, "cannot get clock %s\n", "clk_mac_speed");
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+
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if (bsp_priv->clock_input) {
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dev_info(dev, "clock input from PHY\n");
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} else {
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@@ -1094,6 +1157,9 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
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if (!IS_ERR(bsp_priv->mac_clk_tx))
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clk_prepare_enable(bsp_priv->mac_clk_tx);
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+ if (!IS_ERR(bsp_priv->clk_mac_speed))
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+ clk_prepare_enable(bsp_priv->clk_mac_speed);
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+
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/**
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* if (!IS_ERR(bsp_priv->clk_mac))
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* clk_prepare_enable(bsp_priv->clk_mac);
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@@ -1118,6 +1184,8 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
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clk_disable_unprepare(bsp_priv->pclk_mac);
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clk_disable_unprepare(bsp_priv->mac_clk_tx);
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+
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+ clk_disable_unprepare(bsp_priv->clk_mac_speed);
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/**
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* if (!IS_ERR(bsp_priv->clk_mac))
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* clk_disable_unprepare(bsp_priv->clk_mac);
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@@ -1414,6 +1482,7 @@ static int rk_gmac_resume(struct device *dev)
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static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
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static const struct of_device_id rk_gmac_dwmac_match[] = {
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+ { .compatible = "rockchip,px30-gmac", .data = &px30_ops },
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{ .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
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{ .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
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{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
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