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@@ -787,6 +787,25 @@ clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
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pll->width, CLK_DIVIDER_POWER_OF_TWO);
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}
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+static long
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+clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long *prate)
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+{
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+ struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
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+ u32 ctl, div;
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+
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+ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
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+
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+ ctl >>= PLL_POST_DIV_SHIFT;
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+ ctl &= BIT(pll->width) - 1;
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+ div = 1 << fls(ctl);
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+
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+ if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
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+ *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
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+
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+ return DIV_ROUND_UP_ULL((u64)*prate, div);
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+}
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+
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static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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@@ -807,3 +826,9 @@ const struct clk_ops clk_alpha_pll_postdiv_ops = {
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.set_rate = clk_alpha_pll_postdiv_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
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+
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+const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
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+ .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
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+ .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
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+};
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+EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
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