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@@ -2098,6 +2098,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
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if (IS_CANNONLAKE(dev_priv)) {
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if (IS_CANNONLAKE(dev_priv)) {
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/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
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/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
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val = I915_READ(DPCLKA_CFGCR0);
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val = I915_READ(DPCLKA_CFGCR0);
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+ val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
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val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
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val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
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I915_WRITE(DPCLKA_CFGCR0, val);
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I915_WRITE(DPCLKA_CFGCR0, val);
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