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@@ -4782,8 +4782,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
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/* 2b: Program RC6 thresholds.*/
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/* 2b: Program RC6 thresholds.*/
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/* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
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/* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
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- if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
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- (INTEL_REVID(dev) <= SKL_REVID_E0)))
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+ if (IS_SKYLAKE(dev))
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I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
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I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
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else
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else
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I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
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I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
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@@ -4825,7 +4824,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
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* WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
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* WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
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*/
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*/
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if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
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if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
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- ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0)))
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+ ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0)))
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I915_WRITE(GEN9_PG_ENABLE, 0);
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I915_WRITE(GEN9_PG_ENABLE, 0);
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else
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else
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I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
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I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
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