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@@ -171,10 +171,12 @@ void mt76x2_mac_write_txwi(struct mt76x2_dev *dev, struct mt76x2_txwi *txwi,
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{
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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struct ieee80211_tx_rate *rate = &info->control.rates[0];
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+ struct ieee80211_key_conf *key = info->control.hw_key;
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u16 rate_ht_mask = FIELD_PREP(MT_RXWI_RATE_PHY, BIT(1) | BIT(2));
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u16 txwi_flags = 0;
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u8 nss;
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s8 txpwr_adj, max_txpwr_adj;
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+ u8 ccmp_pn[8];
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memset(txwi, 0, sizeof(*txwi));
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@@ -185,6 +187,20 @@ void mt76x2_mac_write_txwi(struct mt76x2_dev *dev, struct mt76x2_txwi *txwi,
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txwi->pktid = 1;
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+ if (wcid && wcid->sw_iv && key) {
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+ u64 pn = atomic64_inc_return(&key->tx_pn);
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+ ccmp_pn[0] = pn;
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+ ccmp_pn[1] = pn >> 8;
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+ ccmp_pn[2] = 0;
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+ ccmp_pn[3] = 0x20 | (key->keyidx << 6);
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+ ccmp_pn[4] = pn >> 16;
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+ ccmp_pn[5] = pn >> 24;
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+ ccmp_pn[6] = pn >> 32;
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+ ccmp_pn[7] = pn >> 40;
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+ txwi->iv = *((u32 *) &ccmp_pn[0]);
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+ txwi->eiv = *((u32 *) &ccmp_pn[1]);
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+ }
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+
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spin_lock_bh(&dev->mt76.lock);
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if (wcid && (rate->idx < 0 || !rate->count)) {
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txwi->rate = wcid->tx_rate;
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