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@@ -1130,6 +1130,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
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unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
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if (adev->asic_type == CHIP_VEGA10 ||
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+ adev->asic_type == CHIP_VEGA12 ||
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adev->asic_type == CHIP_RAVEN)
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client_id = SOC15_IH_CLIENTID_DCE;
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@@ -1501,6 +1502,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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case CHIP_POLARIS10:
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case CHIP_POLARIS12:
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case CHIP_VEGA10:
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+ case CHIP_VEGA12:
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if (dce110_register_irq_handlers(dm->adev)) {
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DRM_ERROR("DM: Failed to initialize IRQ\n");
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goto fail;
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@@ -1698,6 +1700,7 @@ static int dm_early_init(void *handle)
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adev->mode_info.plane_type = dm_plane_type_default;
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break;
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case CHIP_VEGA10:
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+ case CHIP_VEGA12:
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adev->mode_info.num_crtc = 6;
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adev->mode_info.num_hpd = 6;
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adev->mode_info.num_dig = 6;
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@@ -1945,6 +1948,7 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
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AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
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if (adev->asic_type == CHIP_VEGA10 ||
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+ adev->asic_type == CHIP_VEGA12 ||
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adev->asic_type == CHIP_RAVEN) {
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/* Fill GFX9 params */
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plane_state->tiling_info.gfx9.num_pipes =
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