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@@ -28,7 +28,12 @@
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/* Runtime PM autosuspend timeout: PM is fairly light on this driver */
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#define SPI_AUTOSUSPEND_TIMEOUT 200
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-#define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
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+/* Some SoCs using this driver support up to 8 chip selects.
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+ * It is up to the implementer to only use the chip selects
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+ * that are available.
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+ */
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+#define ORION_NUM_CHIPSELECTS 8
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+
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#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
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#define ORION_SPI_IF_CTRL_REG 0x00
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@@ -44,6 +49,10 @@
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#define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
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#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
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ORION_SPI_MODE_CPHA)
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+#define ORION_SPI_CS_MASK 0x1C
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+#define ORION_SPI_CS_SHIFT 2
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+#define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
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+ ORION_SPI_CS_MASK)
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enum orion_spi_type {
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ORION_SPI,
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@@ -221,6 +230,10 @@ static void orion_spi_set_cs(struct spi_device *spi, bool enable)
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orion_spi = spi_master_get_devdata(spi->master);
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+ orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
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+ orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
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+ ORION_SPI_CS(spi->chip_select));
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+
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/* Chip select logic is inverted from spi_set_cs */
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if (!enable)
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orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
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