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@@ -2568,8 +2568,8 @@ static int tegra210_enable_pllu(void)
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reg |= PLL_ENABLE;
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writel(reg, clk_base + PLLU_BASE);
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- readl_relaxed_poll_timeout(clk_base + PLLU_BASE, reg,
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- reg & PLL_BASE_LOCK, 2, 1000);
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+ readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
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+ reg & PLL_BASE_LOCK, 2, 1000);
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if (!(reg & PLL_BASE_LOCK)) {
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pr_err("Timed out waiting for PLL_U to lock\n");
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return -ETIMEDOUT;
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