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@@ -198,7 +198,6 @@ void omap_sram_idle(void)
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int per_next_state = PWRDM_POWER_ON;
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int core_next_state = PWRDM_POWER_ON;
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int per_going_off;
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- int core_prev_state;
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u32 sdrc_pwr = 0;
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mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
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@@ -278,16 +277,20 @@ void omap_sram_idle(void)
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sdrc_write_reg(sdrc_pwr, SDRC_POWER);
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/* CORE */
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- if (core_next_state < PWRDM_POWER_ON) {
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- core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
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- if (core_prev_state == PWRDM_POWER_OFF) {
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- omap3_core_restore_context();
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- omap3_cm_restore_context();
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- omap3_sram_restore_context();
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- omap2_sms_restore_context();
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- }
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+ if (core_next_state < PWRDM_POWER_ON &&
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+ pwrdm_read_prev_pwrst(core_pwrdm) == PWRDM_POWER_OFF) {
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+ omap3_core_restore_context();
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+ omap3_cm_restore_context();
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+ omap3_sram_restore_context();
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+ omap2_sms_restore_context();
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+ } else {
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+ /*
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+ * In off-mode resume path above, omap3_core_restore_context
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+ * also handles the INTC autoidle restore done here so limit
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+ * this to non-off mode resume paths so we don't do it twice.
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+ */
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+ omap3_intc_resume_idle();
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}
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- omap3_intc_resume_idle();
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pwrdm_post_transition(NULL);
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