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@@ -897,6 +897,23 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
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.field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
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};
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+static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
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+ .has_reset = true,
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+ .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
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+ .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
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+ .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
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+ .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
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+ .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
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+ .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
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+ .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
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+ .has_slave_select_bit = true,
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+ .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
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+ .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
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+ .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
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+ .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
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+ .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
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+};
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+
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static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
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.has_reset = true,
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.reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
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@@ -1120,6 +1137,10 @@ static const struct of_device_id sun4i_i2s_match[] = {
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.compatible = "allwinner,sun6i-a31-i2s",
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.data = &sun6i_a31_i2s_quirks,
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},
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+ {
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+ .compatible = "allwinner,sun8i-a83t-i2s",
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+ .data = &sun8i_a83t_i2s_quirks,
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+ },
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{
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.compatible = "allwinner,sun8i-h3-i2s",
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.data = &sun8i_h3_i2s_quirks,
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