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@@ -12,32 +12,38 @@
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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-#include <linux/init.h>
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-#include <linux/clk.h>
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-#include <linux/serial_8250.h>
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-#include <linux/platform_device.h>
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+
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+#include <linux/clk-provider.h>
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+#include <linux/clk/davinci.h>
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+#include <linux/clkdev.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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-#include <linux/spi/spi.h>
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+#include <linux/init.h>
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#include <linux/platform_data/edma.h>
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#include <linux/platform_data/gpio-davinci.h>
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#include <linux/platform_data/keyscan-davinci.h>
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#include <linux/platform_data/spi-davinci.h>
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+#include <linux/platform_device.h>
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+#include <linux/serial_8250.h>
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+#include <linux/spi/spi.h>
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#include <asm/mach/map.h>
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+#include <mach/common.h>
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#include <mach/cputype.h>
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-#include "psc.h"
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-#include <mach/mux.h>
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#include <mach/irqs.h>
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-#include <mach/time.h>
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+#include <mach/mux.h>
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#include <mach/serial.h>
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-#include <mach/common.h>
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+#include <mach/time.h>
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+#include "asp.h"
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#include "davinci.h"
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-#include "clock.h"
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#include "mux.h"
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-#include "asp.h"
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+
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+#ifndef CONFIG_COMMON_CLK
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+#include "clock.h"
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+#include "psc.h"
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+#endif
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#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
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#define DM365_RTC_BASE 0x01c69000
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@@ -54,6 +60,7 @@
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#define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
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#define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
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+#ifndef CONFIG_COMMON_CLK
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static struct pll_data pll1_data = {
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.num = 1,
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.phys_base = DAVINCI_PLL1_BASE,
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@@ -485,7 +492,7 @@ static struct clk_lookup dm365_clks[] = {
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CLK(NULL, "mjcp", &mjcp_clk),
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CLK(NULL, NULL, NULL),
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};
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-
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+#endif
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/*----------------------------------------------------------------------*/
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#define INTMUX 0x18
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@@ -1171,8 +1178,33 @@ void __init dm365_init(void)
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void __init dm365_init_time(void)
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{
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+#ifdef CONFIG_COMMON_CLK
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+ void __iomem *pll1, *pll2, *psc;
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+ struct clk *clk;
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+
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+ clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
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+
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+ pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
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+ dm365_pll1_init(NULL, pll1, NULL);
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+
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+ pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
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+ dm365_pll2_init(NULL, pll2, NULL);
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+
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+ psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
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+ dm365_psc_init(NULL, psc);
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+
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+ clk = clk_get(NULL, "timer0");
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+
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+ davinci_timer_init(clk);
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+#else
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davinci_clk_init(dm365_clks);
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davinci_timer_init(&timer0_clk);
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+#endif
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+}
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+
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+void __init dm365_register_clocks(void)
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+{
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+ /* all clocks are currently registered in dm365_init_time() */
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}
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static struct resource dm365_vpss_resources[] = {
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