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@@ -7,10 +7,30 @@
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* (at your option) any later version.
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*/
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-#include "hns_dsaf_misc.h"
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#include "hns_dsaf_mac.h"
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-#include "hns_dsaf_reg.h"
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+#include "hns_dsaf_misc.h"
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#include "hns_dsaf_ppe.h"
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+#include "hns_dsaf_reg.h"
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+
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+static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
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+{
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+ if (dsaf_dev->sub_ctrl)
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+ dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
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+ else
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+ dsaf_write_reg(dsaf_dev->sc_base, reg, val);
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+}
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+
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+static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
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+{
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+ u32 ret;
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+
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+ if (dsaf_dev->sub_ctrl)
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+ ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
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+ else
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+ ret = dsaf_read_reg(dsaf_dev->sc_base, reg);
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+
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+ return ret;
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+}
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void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
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u16 speed, int data)
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@@ -22,8 +42,8 @@ void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
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pr_err("sfp_led_opt mac_dev is null!\n");
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return;
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}
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- if (!mac_cb->cpld_vaddr) {
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- dev_err(mac_cb->dev, "mac_id=%d, cpld_vaddr is null !\n",
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+ if (!mac_cb->cpld_ctrl) {
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+ dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
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mac_cb->mac_id);
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return;
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}
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@@ -40,21 +60,24 @@ void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
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dsaf_set_bit(value, DSAF_LED_DATA_B, data);
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if (value != mac_cb->cpld_led_value) {
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- dsaf_write_b(mac_cb->cpld_vaddr, value);
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+ dsaf_write_syscon(mac_cb->cpld_ctrl,
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+ mac_cb->cpld_ctrl_reg, value);
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mac_cb->cpld_led_value = value;
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}
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} else {
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- dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
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+ dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
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+ CPLD_LED_DEFAULT_VALUE);
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mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
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}
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}
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void cpld_led_reset(struct hns_mac_cb *mac_cb)
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{
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- if (!mac_cb || !mac_cb->cpld_vaddr)
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+ if (!mac_cb || !mac_cb->cpld_ctrl)
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return;
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- dsaf_write_b(mac_cb->cpld_vaddr, CPLD_LED_DEFAULT_VALUE);
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+ dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
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+ CPLD_LED_DEFAULT_VALUE);
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mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
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}
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@@ -63,15 +86,19 @@ int cpld_set_led_id(struct hns_mac_cb *mac_cb,
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{
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switch (status) {
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case HNAE_LED_ACTIVE:
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- mac_cb->cpld_led_value = dsaf_read_b(mac_cb->cpld_vaddr);
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+ mac_cb->cpld_led_value =
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+ dsaf_read_syscon(mac_cb->cpld_ctrl,
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+ mac_cb->cpld_ctrl_reg);
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dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
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CPLD_LED_ON_VALUE);
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- dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
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+ dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
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+ mac_cb->cpld_led_value);
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return 2;
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case HNAE_LED_INACTIVE:
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dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
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CPLD_LED_DEFAULT_VALUE);
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- dsaf_write_b(mac_cb->cpld_vaddr, mac_cb->cpld_led_value);
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+ dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
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+ mac_cb->cpld_led_value);
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break;
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default:
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break;
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@@ -95,10 +122,8 @@ void hns_dsaf_rst(struct dsaf_device *dsaf_dev, u32 val)
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nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
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}
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- dsaf_write_reg(dsaf_dev->sc_base, xbar_reg_addr,
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- RESET_REQ_OR_DREQ);
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- dsaf_write_reg(dsaf_dev->sc_base, nt_reg_addr,
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- RESET_REQ_OR_DREQ);
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+ dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
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+ dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
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}
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void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
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@@ -110,14 +135,14 @@ void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
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return;
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reg_val |= RESET_REQ_OR_DREQ;
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- reg_val |= 0x2082082 << port;
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+ reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;
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if (val == 0)
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reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
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else
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reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
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- dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
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+ dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
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}
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void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
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@@ -129,68 +154,63 @@ void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
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if (port >= DSAF_XGE_NUM)
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return;
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- reg_val |= XGMAC_TRX_CORE_SRST_M << port;
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+ reg_val |= XGMAC_TRX_CORE_SRST_M
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+ << dsaf_dev->mac_cb[port]->port_rst_off;
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if (val == 0)
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reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
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else
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reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
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- dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
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+ dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
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}
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void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
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{
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u32 reg_val_1;
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u32 reg_val_2;
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+ u32 port_rst_off;
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if (port >= DSAF_GE_NUM)
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return;
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- if (port < DSAF_SERVICE_NW_NUM) {
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+ if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
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reg_val_1 = 0x1 << port;
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+ port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
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/* there is difference between V1 and V2 in register.*/
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if (AE_IS_VER1(dsaf_dev->dsaf_ver))
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- reg_val_2 = 0x1041041 << port;
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+ reg_val_2 = 0x1041041 << port_rst_off;
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else
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- reg_val_2 = 0x2082082 << port;
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+ reg_val_2 = 0x2082082 << port_rst_off;
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if (val == 0) {
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- dsaf_write_reg(dsaf_dev->sc_base,
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- DSAF_SUB_SC_GE_RESET_REQ1_REG,
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+ dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
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reg_val_1);
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- dsaf_write_reg(dsaf_dev->sc_base,
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- DSAF_SUB_SC_GE_RESET_REQ0_REG,
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+ dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
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reg_val_2);
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} else {
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- dsaf_write_reg(dsaf_dev->sc_base,
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- DSAF_SUB_SC_GE_RESET_DREQ0_REG,
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+ dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
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reg_val_2);
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- dsaf_write_reg(dsaf_dev->sc_base,
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- DSAF_SUB_SC_GE_RESET_DREQ1_REG,
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+ dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
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reg_val_1);
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}
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} else {
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- reg_val_1 = 0x15540 << (port - 6);
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- reg_val_2 = 0x100 << (port - 6);
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+ reg_val_1 = 0x15540 << dsaf_dev->reset_offset;
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+ reg_val_2 = 0x100 << dsaf_dev->reset_offset;
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if (val == 0) {
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- dsaf_write_reg(dsaf_dev->sc_base,
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- DSAF_SUB_SC_GE_RESET_REQ1_REG,
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+ dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
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reg_val_1);
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- dsaf_write_reg(dsaf_dev->sc_base,
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- DSAF_SUB_SC_PPE_RESET_REQ_REG,
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+ dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
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reg_val_2);
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} else {
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- dsaf_write_reg(dsaf_dev->sc_base,
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- DSAF_SUB_SC_GE_RESET_DREQ1_REG,
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+ dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
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reg_val_1);
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- dsaf_write_reg(dsaf_dev->sc_base,
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- DSAF_SUB_SC_PPE_RESET_DREQ_REG,
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+ dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
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reg_val_2);
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}
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}
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@@ -201,24 +221,23 @@ void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, u32 val)
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u32 reg_val = 0;
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u32 reg_addr;
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- reg_val |= RESET_REQ_OR_DREQ << port;
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+ reg_val |= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off;
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if (val == 0)
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reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
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else
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reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
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- dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
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+ dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
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}
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void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
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{
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- int comm_index = ppe_common->comm_index;
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struct dsaf_device *dsaf_dev = ppe_common->dsaf_dev;
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u32 reg_val;
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u32 reg_addr;
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- if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX) {
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+ if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
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reg_val = RESET_REQ_OR_DREQ;
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if (val == 0)
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reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
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@@ -226,7 +245,7 @@ void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
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reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
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} else {
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- reg_val = 0x100 << (comm_index - 1);
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+ reg_val = 0x100 << dsaf_dev->reset_offset;
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if (val == 0)
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reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
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@@ -234,7 +253,7 @@ void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, u32 val)
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reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
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}
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- dsaf_write_reg(dsaf_dev->sc_base, reg_addr, reg_val);
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+ dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
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}
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/**
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@@ -246,36 +265,45 @@ phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
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{
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u32 mode;
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u32 reg;
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- u32 shift;
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bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
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- void __iomem *sys_ctl_vaddr = mac_cb->sys_ctl_vaddr;
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int mac_id = mac_cb->mac_id;
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- phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
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+ phy_interface_t phy_if;
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- if (is_ver1 && (mac_id >= 6 && mac_id <= 7)) {
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- phy_if = PHY_INTERFACE_MODE_SGMII;
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- } else if (mac_id >= 0 && mac_id <= 3) {
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- reg = is_ver1 ? HNS_MAC_HILINK4_REG : HNS_MAC_HILINK4V2_REG;
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- mode = dsaf_read_reg(sys_ctl_vaddr, reg);
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- /* mac_id 0, 1, 2, 3 ---> hilink4 lane 0, 1, 2, 3 */
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- shift = is_ver1 ? 0 : mac_id;
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- if (dsaf_get_bit(mode, shift))
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- phy_if = PHY_INTERFACE_MODE_XGMII;
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+ if (is_ver1) {
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+ if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev))
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+ return PHY_INTERFACE_MODE_SGMII;
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+
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+ if (mac_id >= 0 && mac_id <= 3)
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+ reg = HNS_MAC_HILINK4_REG;
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else
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- phy_if = PHY_INTERFACE_MODE_SGMII;
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- } else if (mac_id >= 4 && mac_id <= 7) {
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- reg = is_ver1 ? HNS_MAC_HILINK3_REG : HNS_MAC_HILINK3V2_REG;
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- mode = dsaf_read_reg(sys_ctl_vaddr, reg);
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- /* mac_id 4, 5, 6, 7 ---> hilink3 lane 2, 3, 0, 1 */
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- shift = is_ver1 ? 0 : mac_id <= 5 ? mac_id - 2 : mac_id - 6;
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- if (dsaf_get_bit(mode, shift))
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- phy_if = PHY_INTERFACE_MODE_XGMII;
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+ reg = HNS_MAC_HILINK3_REG;
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+ } else{
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+ if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3)
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+ reg = HNS_MAC_HILINK4V2_REG;
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else
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- phy_if = PHY_INTERFACE_MODE_SGMII;
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+ reg = HNS_MAC_HILINK3V2_REG;
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}
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+
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+ mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
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+ if (dsaf_get_bit(mode, mac_cb->port_mode_off))
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+ phy_if = PHY_INTERFACE_MODE_XGMII;
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+ else
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+ phy_if = PHY_INTERFACE_MODE_SGMII;
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+
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return phy_if;
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}
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+int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt)
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+{
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+ if (!mac_cb->cpld_ctrl)
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+ return -ENODEV;
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+
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+ *sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
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+ + MAC_SFP_PORT_OFFSET);
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+
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+ return 0;
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+}
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+
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/**
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* hns_mac_config_sds_loopback - set loop back for serdes
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* @mac_cb: mac control block
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@@ -312,7 +340,14 @@ int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, u8 en)
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pr_info("no sfp in this eth\n");
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}
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- dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);
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+ if (mac_cb->serdes_ctrl) {
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+ u32 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
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+
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+ dsaf_set_field(origin, 1ull << 10, 10, !!en);
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+ dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
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+ } else {
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+ dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, !!en);
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+ }
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return 0;
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|
}
|