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@@ -11,6 +11,7 @@
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/include/ "skeleton.dtsi"
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+#include <dt-bindings/clock/r8a7779-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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@@ -25,21 +26,25 @@
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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+ clock-frequency = <1000000000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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+ clock-frequency = <1000000000>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <2>;
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+ clock-frequency = <1000000000>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <3>;
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+ clock-frequency = <1000000000>;
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};
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};
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@@ -157,6 +162,7 @@
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc70000 0x1000>;
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interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
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status = "disabled";
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};
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@@ -166,6 +172,7 @@
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc71000 0x1000>;
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interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
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status = "disabled";
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};
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@@ -175,6 +182,7 @@
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc72000 0x1000>;
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interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
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status = "disabled";
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};
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@@ -184,6 +192,67 @@
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compatible = "renesas,i2c-r8a7779";
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reg = <0xffc73000 0x1000>;
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interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
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+ status = "disabled";
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+ };
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+
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+ scif0: serial@ffe40000 {
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+ compatible = "renesas,scif-r8a7779", "renesas,scif";
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+ reg = <0xffe40000 0x100>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cpg_clocks R8A7779_CLK_P>;
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+ clock-names = "sci_ick";
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+ status = "disabled";
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+ };
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+
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+ scif1: serial@ffe41000 {
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+ compatible = "renesas,scif-r8a7779", "renesas,scif";
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+ reg = <0xffe41000 0x100>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cpg_clocks R8A7779_CLK_P>;
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+ clock-names = "sci_ick";
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+ status = "disabled";
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+ };
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+
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+ scif2: serial@ffe42000 {
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+ compatible = "renesas,scif-r8a7779", "renesas,scif";
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+ reg = <0xffe42000 0x100>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cpg_clocks R8A7779_CLK_P>;
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+ clock-names = "sci_ick";
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+ status = "disabled";
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+ };
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+
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+ scif3: serial@ffe43000 {
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+ compatible = "renesas,scif-r8a7779", "renesas,scif";
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+ reg = <0xffe43000 0x100>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cpg_clocks R8A7779_CLK_P>;
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+ clock-names = "sci_ick";
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+ status = "disabled";
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+ };
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+
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+ scif4: serial@ffe44000 {
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+ compatible = "renesas,scif-r8a7779", "renesas,scif";
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+ reg = <0xffe44000 0x100>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cpg_clocks R8A7779_CLK_P>;
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+ clock-names = "sci_ick";
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+ status = "disabled";
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+ };
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+
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+ scif5: serial@ffe45000 {
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+ compatible = "renesas,scif-r8a7779", "renesas,scif";
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+ reg = <0xffe45000 0x100>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cpg_clocks R8A7779_CLK_P>;
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+ clock-names = "sci_ick";
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status = "disabled";
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};
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@@ -201,12 +270,14 @@
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compatible = "renesas,rcar-sata";
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reg = <0xfc600000 0x2000>;
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interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp1_clks R8A7779_CLK_SATA>;
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};
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sdhi0: sd@ffe4c000 {
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4c000 0x100>;
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interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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@@ -216,6 +287,7 @@
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4d000 0x100>;
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interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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@@ -225,6 +297,7 @@
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4e000 0x100>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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@@ -234,6 +307,7 @@
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compatible = "renesas,sdhi-r8a7779";
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reg = <0xffe4f000 0x100>;
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
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cap-sd-highspeed;
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cap-sdio-irq;
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status = "disabled";
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@@ -245,6 +319,7 @@
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interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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+ clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
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status = "disabled";
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};
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@@ -254,6 +329,7 @@
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interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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+ clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
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status = "disabled";
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};
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@@ -263,6 +339,150 @@
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interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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+ clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
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status = "disabled";
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};
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+
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+ clocks {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+
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+ /* External root clock */
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+ extal_clk: extal_clk {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ /* This value must be overriden by the board. */
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+ clock-frequency = <0>;
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+ clock-output-names = "extal";
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+ };
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+
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+ /* Special CPG clocks */
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+ cpg_clocks: clocks@ffc80000 {
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+ compatible = "renesas,r8a7779-cpg-clocks";
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+ reg = <0xffc80000 0x30>;
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+ clocks = <&extal_clk>;
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+ #clock-cells = <1>;
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+ clock-output-names = "plla", "z", "zs", "s",
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+ "s1", "p", "b", "out";
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+ };
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+
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+ /* Fixed factor clocks */
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+ i_clk: i_clk {
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+ compatible = "fixed-factor-clock";
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+ clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
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+ #clock-cells = <0>;
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+ clock-div = <2>;
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+ clock-mult = <1>;
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+ clock-output-names = "i";
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+ };
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+ s3_clk: s3_clk {
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+ compatible = "fixed-factor-clock";
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+ clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
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+ #clock-cells = <0>;
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+ clock-div = <8>;
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+ clock-mult = <1>;
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+ clock-output-names = "s3";
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+ };
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+ s4_clk: s4_clk {
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+ compatible = "fixed-factor-clock";
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+ clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
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+ #clock-cells = <0>;
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+ clock-div = <16>;
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+ clock-mult = <1>;
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+ clock-output-names = "s4";
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+ };
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+ g_clk: g_clk {
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+ compatible = "fixed-factor-clock";
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+ clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
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+ #clock-cells = <0>;
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+ clock-div = <24>;
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+ clock-mult = <1>;
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+ clock-output-names = "g";
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+ };
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+
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+ /* Gate clocks */
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+ mstp0_clks: clocks@ffc80030 {
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+ compatible = "renesas,r8a7779-mstp-clocks",
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+ "renesas,cpg-mstp-clocks";
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+ reg = <0xffc80030 4>;
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+ clocks = <&cpg_clocks R8A7779_CLK_S>,
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+ <&cpg_clocks R8A7779_CLK_P>,
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+ <&cpg_clocks R8A7779_CLK_P>,
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+ <&cpg_clocks R8A7779_CLK_P>,
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+ <&cpg_clocks R8A7779_CLK_S>,
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+ <&cpg_clocks R8A7779_CLK_S>,
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+ <&cpg_clocks R8A7779_CLK_S1>,
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+ <&cpg_clocks R8A7779_CLK_S1>,
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+ <&cpg_clocks R8A7779_CLK_S1>,
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+ <&cpg_clocks R8A7779_CLK_S1>,
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+ <&cpg_clocks R8A7779_CLK_S1>,
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+ <&cpg_clocks R8A7779_CLK_S1>,
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+ <&cpg_clocks R8A7779_CLK_P>,
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+ <&cpg_clocks R8A7779_CLK_P>,
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+ <&cpg_clocks R8A7779_CLK_P>,
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+ <&cpg_clocks R8A7779_CLK_P>;
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+ #clock-cells = <1>;
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+ renesas,clock-indices = <
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+ R8A7779_CLK_HSPI R8A7779_CLK_TMU2
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+ R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
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+ R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
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+ R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
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+ R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
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+ R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
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+ R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
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+ R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
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+ >;
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+ clock-output-names =
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+ "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
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+ "hscif0", "scif5", "scif4", "scif3", "scif2",
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+ "scif1", "scif0", "i2c3", "i2c2", "i2c1",
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+ "i2c0";
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+ };
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+ mstp1_clks: clocks@ffc80034 {
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+ compatible = "renesas,r8a7779-mstp-clocks",
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+ "renesas,cpg-mstp-clocks";
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+ reg = <0xffc80034 4>, <0xffc80044 4>;
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+ clocks = <&cpg_clocks R8A7779_CLK_P>,
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+ <&cpg_clocks R8A7779_CLK_P>,
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+ <&cpg_clocks R8A7779_CLK_S>,
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+ <&cpg_clocks R8A7779_CLK_S>,
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+ <&cpg_clocks R8A7779_CLK_S>,
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+ <&cpg_clocks R8A7779_CLK_S>,
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+ <&cpg_clocks R8A7779_CLK_P>,
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+ <&cpg_clocks R8A7779_CLK_P>,
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+ <&cpg_clocks R8A7779_CLK_P>,
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+ <&cpg_clocks R8A7779_CLK_S>;
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+ #clock-cells = <1>;
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+ renesas,clock-indices = <
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+ R8A7779_CLK_USB01 R8A7779_CLK_USB2
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+ R8A7779_CLK_DU R8A7779_CLK_VIN2
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+ R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
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+ R8A7779_CLK_ETHER R8A7779_CLK_SATA
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+ R8A7779_CLK_PCIE R8A7779_CLK_VIN3
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+ >;
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+ clock-output-names =
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+ "usb01", "usb2",
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+ "du", "vin2",
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+ "vin1", "vin0",
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+ "ether", "sata",
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+ "pcie", "vin3";
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+ };
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+ mstp3_clks: clocks@ffc8003c {
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+ compatible = "renesas,r8a7779-mstp-clocks",
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+ "renesas,cpg-mstp-clocks";
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+ reg = <0xffc8003c 4>;
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+ clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
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+ <&s4_clk>, <&s4_clk>;
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+ #clock-cells = <1>;
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+ renesas,clock-indices = <
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+ R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
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+ R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
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+ R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
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+ >;
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+ clock-output-names =
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+ "sdhi3", "sdhi2", "sdhi1", "sdhi0",
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+ "mmc1", "mmc0";
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+ };
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+ };
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};
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