|
@@ -353,7 +353,8 @@ static int tegra_dma_slave_config(struct dma_chan *dc,
|
|
|
}
|
|
|
|
|
|
memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
|
|
|
- if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID) {
|
|
|
+ if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID &&
|
|
|
+ sconfig->device_fc) {
|
|
|
if (sconfig->slave_id > TEGRA_APBDMA_CSR_REQ_SEL_MASK)
|
|
|
return -EINVAL;
|
|
|
tdc->slave_id = sconfig->slave_id;
|
|
@@ -970,8 +971,13 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
|
|
|
TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
|
|
|
ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
|
|
|
|
|
|
- csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
|
|
|
- csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
|
|
|
+ csr |= TEGRA_APBDMA_CSR_ONCE;
|
|
|
+
|
|
|
+ if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
|
|
|
+ csr |= TEGRA_APBDMA_CSR_FLOW;
|
|
|
+ csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
|
|
|
+ }
|
|
|
+
|
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
|
csr |= TEGRA_APBDMA_CSR_IE_EOC;
|
|
|
|
|
@@ -1110,10 +1116,13 @@ static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
|
|
|
TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
|
|
|
ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
|
|
|
|
|
|
- csr |= TEGRA_APBDMA_CSR_FLOW;
|
|
|
+ if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
|
|
|
+ csr |= TEGRA_APBDMA_CSR_FLOW;
|
|
|
+ csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
|
|
|
+ }
|
|
|
+
|
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
|
csr |= TEGRA_APBDMA_CSR_IE_EOC;
|
|
|
- csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
|
|
|
|
|
|
apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
|
|
|
|