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@@ -201,8 +201,8 @@ struct pxa3xx_nand_info {
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int use_spare; /* use spare ? */
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int is_ready;
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- unsigned int page_size; /* page size of attached chip */
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- unsigned int data_size; /* data size in FIFO */
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+ unsigned int fifo_size; /* max. data size in the FIFO */
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+ unsigned int data_size; /* data to be read from FIFO */
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unsigned int oob_size;
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int retcode;
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@@ -303,16 +303,15 @@ static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
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static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
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{
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- struct pxa3xx_nand_host *host = info->host[info->cs];
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int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
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- info->data_size = host->page_size;
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+ info->data_size = info->fifo_size;
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if (!oob_enable) {
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info->oob_size = 0;
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return;
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}
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- switch (host->page_size) {
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+ switch (info->fifo_size) {
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case 2048:
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info->oob_size = (info->use_ecc) ? 40 : 64;
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break;
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@@ -929,9 +928,12 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
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uint32_t ndcr = nand_readl(info, NDCR);
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if (ndcr & NDCR_PAGE_SZ) {
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+ /* Controller's FIFO size */
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+ info->fifo_size = 2048;
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host->page_size = 2048;
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host->read_id_bytes = 4;
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} else {
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+ info->fifo_size = 512;
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host->page_size = 512;
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host->read_id_bytes = 2;
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}
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