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@@ -547,14 +547,14 @@ static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
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pm_runtime_get_sync(mcasp->dev);
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switch (div_id) {
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- case 0: /* MCLK divider */
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+ case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
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mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
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AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
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mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
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AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
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break;
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- case 1: /* BCLK divider */
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+ case MCASP_CLKDIV_BCLK: /* BCLK divider */
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mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
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ACLKXDIV(div - 1), ACLKXDIV_MASK);
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mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
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@@ -563,7 +563,8 @@ static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
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mcasp->bclk_div = div;
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break;
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- case 2: /*
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+ case MCASP_CLKDIV_BCLK_FS_RATIO:
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+ /*
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* BCLK/LRCLK ratio descries how many bit-clock cycles
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* fit into one frame. The clock ratio is given for a
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* full period of data (for I2S format both left and
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