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@@ -1252,6 +1252,71 @@ static void si_invalidate_hdp(struct amdgpu_device *adev,
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}
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}
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+static int si_get_pcie_lanes(struct amdgpu_device *adev)
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+{
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+ u32 link_width_cntl;
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+
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+ if (adev->flags & AMD_IS_APU)
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+ return 0;
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+
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+ link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
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+
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+ switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) {
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+ case LC_LINK_WIDTH_X1:
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+ return 1;
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+ case LC_LINK_WIDTH_X2:
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+ return 2;
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+ case LC_LINK_WIDTH_X4:
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+ return 4;
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+ case LC_LINK_WIDTH_X8:
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+ return 8;
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+ case LC_LINK_WIDTH_X0:
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+ case LC_LINK_WIDTH_X16:
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+ default:
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+ return 16;
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+ }
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+}
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+
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+static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes)
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+{
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+ u32 link_width_cntl, mask;
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+
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+ if (adev->flags & AMD_IS_APU)
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+ return;
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+
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+ switch (lanes) {
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+ case 0:
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+ mask = LC_LINK_WIDTH_X0;
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+ break;
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+ case 1:
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+ mask = LC_LINK_WIDTH_X1;
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+ break;
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+ case 2:
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+ mask = LC_LINK_WIDTH_X2;
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+ break;
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+ case 4:
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+ mask = LC_LINK_WIDTH_X4;
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+ break;
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+ case 8:
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+ mask = LC_LINK_WIDTH_X8;
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+ break;
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+ case 16:
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+ mask = LC_LINK_WIDTH_X16;
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+ break;
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+ default:
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+ DRM_ERROR("invalid pcie lane request: %d\n", lanes);
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+ return;
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+ }
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+
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+ link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
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+ link_width_cntl &= ~LC_LINK_WIDTH_MASK;
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+ link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT;
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+ link_width_cntl |= (LC_RECONFIG_NOW |
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+ LC_RECONFIG_ARC_MISSING_ESCAPE);
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+
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+ WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
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+}
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+
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static const struct amdgpu_asic_funcs si_asic_funcs =
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{
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.read_disabled_bios = &si_read_disabled_bios,
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@@ -1262,6 +1327,8 @@ static const struct amdgpu_asic_funcs si_asic_funcs =
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.get_xclk = &si_get_xclk,
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.set_uvd_clocks = &si_set_uvd_clocks,
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.set_vce_clocks = NULL,
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+ .get_pcie_lanes = &si_get_pcie_lanes,
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+ .set_pcie_lanes = &si_set_pcie_lanes,
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.get_config_memsize = &si_get_config_memsize,
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.flush_hdp = &si_flush_hdp,
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.invalidate_hdp = &si_invalidate_hdp,
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