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@@ -1056,36 +1056,36 @@ static void radeon_check_arguments(struct radeon_device *rdev)
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if (!radeon_check_pot_argument(radeon_vm_size)) {
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dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
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radeon_vm_size);
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- radeon_vm_size = 4096;
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+ radeon_vm_size = 4;
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}
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- if (radeon_vm_size < 4) {
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- dev_warn(rdev->dev, "VM size (%d) to small, min is 4MB\n",
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+ if (radeon_vm_size < 1) {
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+ dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n",
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radeon_vm_size);
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- radeon_vm_size = 4096;
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+ radeon_vm_size = 4;
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}
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/*
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* Max GPUVM size for Cayman, SI and CI are 40 bits.
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*/
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- if (radeon_vm_size > 1024*1024) {
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- dev_warn(rdev->dev, "VM size (%d) to large, max is 1TB\n",
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+ if (radeon_vm_size > 1024) {
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+ dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
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radeon_vm_size);
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- radeon_vm_size = 4096;
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+ radeon_vm_size = 4;
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}
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/* defines number of bits in page table versus page directory,
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* a page is 4KB so we have 12 bits offset, minimum 9 bits in the
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* page table and the remaining bits are in the page directory */
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if (radeon_vm_block_size < 9) {
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- dev_warn(rdev->dev, "VM page table size (%d) to small\n",
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+ dev_warn(rdev->dev, "VM page table size (%d) too small\n",
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radeon_vm_block_size);
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radeon_vm_block_size = 9;
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}
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if (radeon_vm_block_size > 24 ||
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- radeon_vm_size < (1ull << radeon_vm_block_size)) {
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- dev_warn(rdev->dev, "VM page table size (%d) to large\n",
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+ (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
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+ dev_warn(rdev->dev, "VM page table size (%d) too large\n",
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radeon_vm_block_size);
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radeon_vm_block_size = 9;
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}
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@@ -1238,7 +1238,7 @@ int radeon_device_init(struct radeon_device *rdev,
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/* Adjust VM size here.
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* Max GPUVM size for cayman+ is 40 bits.
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*/
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- rdev->vm_manager.max_pfn = radeon_vm_size << 8;
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+ rdev->vm_manager.max_pfn = radeon_vm_size << 18;
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/* Set asic functions */
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r = radeon_asic_init(rdev);
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