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@@ -1429,18 +1429,7 @@ static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
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return 0;
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}
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-static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu,
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- unsigned int offset, void *p_data, unsigned int bytes)
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-{
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- struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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-
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- mmio_hw_access_pre(dev_priv);
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- vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
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- mmio_hw_access_post(dev_priv);
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- return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
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-}
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-
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-static int instdone_mmio_read(struct intel_vgpu *vgpu,
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+static int mmio_read_from_hw(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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@@ -1637,9 +1626,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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#undef RING_REG
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#define RING_REG(base) (base + 0x6c)
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- MMIO_RING_DFH(RING_REG, D_ALL, 0, instdone_mmio_read, NULL);
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+ MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
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#undef RING_REG
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- MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, instdone_mmio_read, NULL);
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+ MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
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MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);
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MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
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@@ -1663,9 +1652,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
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MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
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NULL, NULL);
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MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
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- ring_timestamp_mmio_read, NULL);
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+ mmio_read_from_hw, NULL);
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MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
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- ring_timestamp_mmio_read, NULL);
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+ mmio_read_from_hw, NULL);
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MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
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