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@@ -88,7 +88,7 @@ void xhci_quiesce(struct xhci_hcd *xhci)
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cmd = readl(&xhci->op_regs->command);
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cmd &= mask;
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- xhci_writel(xhci, cmd, &xhci->op_regs->command);
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+ writel(cmd, &xhci->op_regs->command);
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}
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/*
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@@ -128,7 +128,7 @@ static int xhci_start(struct xhci_hcd *xhci)
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temp |= (CMD_RUN);
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xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
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temp);
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- xhci_writel(xhci, temp, &xhci->op_regs->command);
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+ writel(temp, &xhci->op_regs->command);
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/*
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* Wait for the HCHalted Status bit to be 0 to indicate the host is
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@@ -167,7 +167,7 @@ int xhci_reset(struct xhci_hcd *xhci)
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xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
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command = readl(&xhci->op_regs->command);
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command |= CMD_RESET;
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- xhci_writel(xhci, command, &xhci->op_regs->command);
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+ writel(command, &xhci->op_regs->command);
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ret = xhci_handshake(xhci, &xhci->op_regs->command,
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CMD_RESET, 0, 10 * 1000 * 1000);
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@@ -614,21 +614,20 @@ int xhci_run(struct usb_hcd *hcd)
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temp = readl(&xhci->ir_set->irq_control);
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temp &= ~ER_IRQ_INTERVAL_MASK;
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temp |= (u32) 160;
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- xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
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+ writel(temp, &xhci->ir_set->irq_control);
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/* Set the HCD state before we enable the irqs */
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temp = readl(&xhci->op_regs->command);
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temp |= (CMD_EIE);
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xhci_dbg_trace(xhci, trace_xhci_dbg_init,
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"// Enable interrupts, cmd = 0x%x.", temp);
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- xhci_writel(xhci, temp, &xhci->op_regs->command);
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+ writel(temp, &xhci->op_regs->command);
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temp = readl(&xhci->ir_set->irq_pending);
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xhci_dbg_trace(xhci, trace_xhci_dbg_init,
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"// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
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xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
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- xhci_writel(xhci, ER_IRQ_ENABLE(temp),
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- &xhci->ir_set->irq_pending);
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+ writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
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xhci_print_ir_set(xhci, 0);
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if (xhci->quirks & XHCI_NEC_HOST)
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@@ -699,10 +698,9 @@ void xhci_stop(struct usb_hcd *hcd)
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xhci_dbg_trace(xhci, trace_xhci_dbg_init,
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"// Disabling event ring interrupts");
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temp = readl(&xhci->op_regs->status);
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- xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
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+ writel(temp & ~STS_EINT, &xhci->op_regs->status);
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temp = readl(&xhci->ir_set->irq_pending);
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- xhci_writel(xhci, ER_IRQ_DISABLE(temp),
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- &xhci->ir_set->irq_pending);
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+ writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
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xhci_print_ir_set(xhci, 0);
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xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
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@@ -762,15 +760,15 @@ static void xhci_save_registers(struct xhci_hcd *xhci)
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static void xhci_restore_registers(struct xhci_hcd *xhci)
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{
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- xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
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- xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
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+ writel(xhci->s3.command, &xhci->op_regs->command);
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+ writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
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xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
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- xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
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- xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
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+ writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
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+ writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
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xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
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xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
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- xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
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- xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
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+ writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
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+ writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
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}
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static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
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@@ -868,7 +866,7 @@ int xhci_suspend(struct xhci_hcd *xhci)
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/* step 2: clear Run/Stop bit */
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command = readl(&xhci->op_regs->command);
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command &= ~CMD_RUN;
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- xhci_writel(xhci, command, &xhci->op_regs->command);
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+ writel(command, &xhci->op_regs->command);
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/* Some chips from Fresco Logic need an extraordinary delay */
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delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
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@@ -887,7 +885,7 @@ int xhci_suspend(struct xhci_hcd *xhci)
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/* step 4: set CSS flag */
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command = readl(&xhci->op_regs->command);
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command |= CMD_CSS;
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- xhci_writel(xhci, command, &xhci->op_regs->command);
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+ writel(command, &xhci->op_regs->command);
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if (xhci_handshake(xhci, &xhci->op_regs->status,
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STS_SAVE, 0, 10 * 1000)) {
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xhci_warn(xhci, "WARN: xHC save state timeout\n");
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@@ -953,7 +951,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
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/* step 3: set CRS flag */
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command = readl(&xhci->op_regs->command);
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command |= CMD_CRS;
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- xhci_writel(xhci, command, &xhci->op_regs->command);
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+ writel(command, &xhci->op_regs->command);
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if (xhci_handshake(xhci, &xhci->op_regs->status,
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STS_RESTORE, 0, 10 * 1000)) {
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xhci_warn(xhci, "WARN: xHC restore state timeout\n");
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@@ -985,10 +983,9 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
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xhci_dbg(xhci, "// Disabling event ring interrupts\n");
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temp = readl(&xhci->op_regs->status);
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- xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
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+ writel(temp & ~STS_EINT, &xhci->op_regs->status);
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temp = readl(&xhci->ir_set->irq_pending);
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- xhci_writel(xhci, ER_IRQ_DISABLE(temp),
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- &xhci->ir_set->irq_pending);
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+ writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
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xhci_print_ir_set(xhci, 0);
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xhci_dbg(xhci, "cleaning up memory\n");
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@@ -1025,7 +1022,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
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/* step 4: set Run/Stop bit */
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command = readl(&xhci->op_regs->command);
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command |= CMD_RUN;
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- xhci_writel(xhci, command, &xhci->op_regs->command);
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+ writel(command, &xhci->op_regs->command);
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xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT,
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0, 250 * 1000);
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@@ -4082,7 +4079,7 @@ int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
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spin_lock_irqsave(&xhci->lock, flags);
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hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
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- xhci_writel(xhci, hlpm_val, hlpm_addr);
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+ writel(hlpm_val, hlpm_addr);
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/* flush write */
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readl(hlpm_addr);
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} else {
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@@ -4091,15 +4088,15 @@ int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
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pm_val &= ~PORT_HIRD_MASK;
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pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
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- xhci_writel(xhci, pm_val, pm_addr);
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+ writel(pm_val, pm_addr);
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pm_val = readl(pm_addr);
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pm_val |= PORT_HLE;
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- xhci_writel(xhci, pm_val, pm_addr);
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+ writel(pm_val, pm_addr);
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/* flush write */
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readl(pm_addr);
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} else {
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pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
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- xhci_writel(xhci, pm_val, pm_addr);
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+ writel(pm_val, pm_addr);
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/* flush write */
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readl(pm_addr);
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if (udev->usb2_hw_lpm_besl_capable) {
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