|
@@ -455,7 +455,7 @@ static void dsi_pll_28nm_save_state(struct msm_dsi_pll *pll)
|
|
|
cached_state->postdiv1 =
|
|
|
pll_read(base + REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG);
|
|
|
cached_state->byte_mux = pll_read(base + REG_DSI_28nm_PHY_PLL_VREG_CFG);
|
|
|
- cached_state->vco_rate = __clk_get_rate(pll->clk_hw.clk);
|
|
|
+ cached_state->vco_rate = clk_hw_get_rate(&pll->clk_hw);
|
|
|
}
|
|
|
|
|
|
static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
|
|
@@ -466,7 +466,7 @@ static int dsi_pll_28nm_restore_state(struct msm_dsi_pll *pll)
|
|
|
int ret;
|
|
|
|
|
|
if ((cached_state->vco_rate != 0) &&
|
|
|
- (cached_state->vco_rate == __clk_get_rate(pll->clk_hw.clk))) {
|
|
|
+ (cached_state->vco_rate == clk_hw_get_rate(&pll->clk_hw))) {
|
|
|
ret = dsi_pll_28nm_clk_set_rate(&pll->clk_hw,
|
|
|
cached_state->vco_rate, 0);
|
|
|
if (ret) {
|