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@@ -2488,11 +2488,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
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return ret;
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}
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-static void i915_error_wake_up(struct drm_i915_private *dev_priv,
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- bool reset_completed)
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+static void i915_error_wake_up(struct drm_i915_private *dev_priv)
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{
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- struct intel_engine_cs *engine;
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-
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/*
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* Notify all waiters for GPU completion events that reset state has
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* been changed, and that they need to restart their wait after
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@@ -2501,18 +2498,10 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
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*/
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/* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
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- for_each_engine(engine, dev_priv)
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- wake_up_all(&engine->irq_queue);
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+ wake_up_all(&dev_priv->gpu_error.wait_queue);
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/* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
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wake_up_all(&dev_priv->pending_flip_queue);
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-
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- /*
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- * Signal tasks blocked in i915_gem_wait_for_error that the pending
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- * reset state is cleared.
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- */
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- if (reset_completed)
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- wake_up_all(&dev_priv->gpu_error.reset_queue);
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}
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/**
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@@ -2577,7 +2566,7 @@ static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
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* Note: The wake_up also serves as a memory barrier so that
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* waiters see the update value of the reset counter atomic_t.
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*/
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- i915_error_wake_up(dev_priv, true);
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+ wake_up_all(&dev_priv->gpu_error.reset_queue);
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}
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}
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@@ -2714,7 +2703,7 @@ void i915_handle_error(struct drm_i915_private *dev_priv,
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* ensure that the waiters see the updated value of the reset
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* counter atomic_t.
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*/
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- i915_error_wake_up(dev_priv, false);
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+ i915_error_wake_up(dev_priv);
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}
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i915_reset_and_wakeup(dev_priv);
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