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@@ -703,25 +703,6 @@ out:
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return IRQ_HANDLED;
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}
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-static void imx_disable_rx_int(struct imx_port *sport)
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-{
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- unsigned long temp;
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-
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- /* disable the receiver ready and aging timer interrupts */
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- temp = readl(sport->port.membase + UCR1);
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- temp &= ~(UCR1_RRDYEN);
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- writel(temp, sport->port.membase + UCR1);
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-
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- temp = readl(sport->port.membase + UCR2);
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- temp &= ~(UCR2_ATEN);
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- writel(temp, sport->port.membase + UCR2);
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-
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- /* disable the rx errors interrupts */
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- temp = readl(sport->port.membase + UCR4);
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- temp &= ~UCR4_OREN;
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- writel(temp, sport->port.membase + UCR4);
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-}
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-
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static void clear_rx_errors(struct imx_port *sport);
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/*
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@@ -1252,18 +1233,21 @@ static int imx_startup(struct uart_port *port)
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if (sport->dma_is_inited && !sport->dma_is_enabled)
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imx_enable_dma(sport);
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- temp = readl(sport->port.membase + UCR1);
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- temp |= UCR1_RRDYEN | UCR1_UARTEN;
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+ temp = readl(sport->port.membase + UCR1) & ~UCR1_RRDYEN;
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+ if (!sport->dma_is_enabled)
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+ temp |= UCR1_RRDYEN;
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+ temp |= UCR1_UARTEN;
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if (sport->have_rtscts)
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temp |= UCR1_RTSDEN;
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writel(temp, sport->port.membase + UCR1);
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- temp = readl(sport->port.membase + UCR4);
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- temp |= UCR4_OREN;
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+ temp = readl(sport->port.membase + UCR4) & ~UCR4_OREN;
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+ if (!sport->dma_is_enabled)
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+ temp |= UCR4_OREN;
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writel(temp, sport->port.membase + UCR4);
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- temp = readl(sport->port.membase + UCR2);
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+ temp = readl(sport->port.membase + UCR2) & ~UCR2_ATEN;
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temp |= (UCR2_RXEN | UCR2_TXEN);
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if (!sport->have_rtscts)
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temp |= UCR2_IRTS;
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@@ -1297,10 +1281,8 @@ static int imx_startup(struct uart_port *port)
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* In our iMX53 the average delay for the first reception dropped from
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* approximately 35000 microseconds to 1000 microseconds.
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*/
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- if (sport->dma_is_enabled) {
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- imx_disable_rx_int(sport);
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+ if (sport->dma_is_enabled)
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start_rx_dma(sport);
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- }
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spin_unlock_irqrestore(&sport->port.lock, flags);
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