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@@ -929,6 +929,37 @@ static bool cik_read_disabled_bios(struct amdgpu_device *adev)
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return r;
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}
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+static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
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+ u8 *bios, u32 length_bytes)
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+{
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+ u32 *dw_ptr;
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+ unsigned long flags;
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+ u32 i, length_dw;
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+
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+ if (bios == NULL)
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+ return false;
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+ if (length_bytes == 0)
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+ return false;
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+ /* APU vbios image is part of sbios image */
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+ if (adev->flags & AMD_IS_APU)
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+ return false;
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+
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+ dw_ptr = (u32 *)bios;
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+ length_dw = ALIGN(length_bytes, 4) / 4;
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+ /* take the smc lock since we are using the smc index */
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+ spin_lock_irqsave(&adev->smc_idx_lock, flags);
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+ /* set rom index to 0 */
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+ WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
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+ WREG32(mmSMC_IND_DATA_0, 0);
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+ /* set index to data for continous read */
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+ WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
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+ for (i = 0; i < length_dw; i++)
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+ dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
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+ spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
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+
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+ return true;
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+}
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+
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static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
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{mmGRBM_STATUS, false},
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{mmGB_ADDR_CONFIG, false},
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@@ -2267,6 +2298,7 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
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static const struct amdgpu_asic_funcs cik_asic_funcs =
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{
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.read_disabled_bios = &cik_read_disabled_bios,
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+ .read_bios_from_rom = &cik_read_bios_from_rom,
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.read_register = &cik_read_register,
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.reset = &cik_asic_reset,
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.set_vga_state = &cik_vga_set_state,
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