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@@ -129,7 +129,7 @@ static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 reg)
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writel(val, port->reg_base + reg);
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}
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-static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *port)
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+static inline bool xilinx_pcie_link_up(struct xilinx_pcie_port *port)
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{
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return (pcie_read(port, XILINX_PCIE_REG_PSCR) &
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XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
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@@ -165,7 +165,7 @@ static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
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/* Check if link is up when trying to access downstream ports */
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if (bus->number != port->root_busno)
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- if (!xilinx_pcie_link_is_up(port))
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+ if (!xilinx_pcie_link_up(port))
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return false;
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/* Only one device down on each root port */
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@@ -541,7 +541,7 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
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{
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struct device *dev = port->dev;
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- if (xilinx_pcie_link_is_up(port))
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+ if (xilinx_pcie_link_up(port))
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dev_info(dev, "PCIe Link is UP\n");
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else
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dev_info(dev, "PCIe Link is DOWN\n");
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