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@@ -97,8 +97,6 @@ static int sch_gpio_core_direction_out(struct gpio_chip *gc,
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u8 curr_dirs;
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unsigned short offset, bit;
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- sch_gpio_core_set(gc, gpio_num, val);
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-
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spin_lock(&gpio_lock);
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offset = CGIO + gpio_num / 8;
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@@ -109,6 +107,17 @@ static int sch_gpio_core_direction_out(struct gpio_chip *gc,
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outb(curr_dirs & ~(1 << bit), gpio_ba + offset);
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spin_unlock(&gpio_lock);
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+
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+ /*
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+ * according to the datasheet, writing to the level register has no
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+ * effect when GPIO is programmed as input.
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+ * Actually the the level register is read-only when configured as input.
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+ * Thus presetting the output level before switching to output is _NOT_ possible.
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+ * Hence we set the level after configuring the GPIO as output.
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+ * But we cannot prevent a short low pulse if direction is set to high
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+ * and an external pull-up is connected.
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+ */
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+ sch_gpio_core_set(gc, gpio_num, val);
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return 0;
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}
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@@ -178,8 +187,6 @@ static int sch_gpio_resume_direction_out(struct gpio_chip *gc,
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u8 curr_dirs;
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unsigned short offset, bit;
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- sch_gpio_resume_set(gc, gpio_num, val);
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-
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offset = RGIO + gpio_num / 8;
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bit = gpio_num % 8;
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@@ -190,6 +197,17 @@ static int sch_gpio_resume_direction_out(struct gpio_chip *gc,
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outb(curr_dirs & ~(1 << bit), gpio_ba + offset);
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spin_unlock(&gpio_lock);
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+
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+ /*
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+ * according to the datasheet, writing to the level register has no
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+ * effect when GPIO is programmed as input.
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+ * Actually the the level register is read-only when configured as input.
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+ * Thus presetting the output level before switching to output is _NOT_ possible.
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+ * Hence we set the level after configuring the GPIO as output.
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+ * But we cannot prevent a short low pulse if direction is set to high
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+ * and an external pull-up is connected.
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+ */
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+ sch_gpio_resume_set(gc, gpio_num, val);
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return 0;
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}
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