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@@ -30,19 +30,20 @@
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#include <video/mipi_display.h>
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#define DSI_VERSION 0x00
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+
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#define DSI_PWR_UP 0x04
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#define RESET 0
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#define POWERUP BIT(0)
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#define DSI_CLKMGR_CFG 0x08
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-#define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8)
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-#define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0)
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+#define TO_CLK_DIVISION(div) (((div) & 0xff) << 8)
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+#define TX_ESC_CLK_DIVISION(div) ((div) & 0xff)
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#define DSI_DPI_VCID 0x0c
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-#define DPI_VID(vid) (((vid) & 0x3) << 0)
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+#define DPI_VCID(vcid) ((vcid) & 0x3)
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#define DSI_DPI_COLOR_CODING 0x10
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-#define EN18_LOOSELY BIT(8)
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+#define LOOSELY18_EN BIT(8)
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#define DPI_COLOR_CODING_16BIT_1 0x0
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#define DPI_COLOR_CODING_16BIT_2 0x1
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#define DPI_COLOR_CODING_16BIT_3 0x2
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@@ -61,22 +62,25 @@
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#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
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#define INVACT_LPCMD_TIME(p) ((p) & 0xff)
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+#define DSI_DBI_VCID 0x1c
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#define DSI_DBI_CFG 0x20
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+#define DSI_DBI_PARTITIONING_EN 0x24
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#define DSI_DBI_CMDSIZE 0x28
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#define DSI_PCKHDL_CFG 0x2c
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-#define EN_CRC_RX BIT(4)
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-#define EN_ECC_RX BIT(3)
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-#define EN_BTA BIT(2)
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-#define EN_EOTP_RX BIT(1)
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-#define EN_EOTP_TX BIT(0)
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+#define CRC_RX_EN BIT(4)
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+#define ECC_RX_EN BIT(3)
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+#define BTA_EN BIT(2)
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+#define EOTP_RX_EN BIT(1)
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+#define EOTP_TX_EN BIT(0)
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+
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+#define DSI_GEN_VCID 0x30
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#define DSI_MODE_CFG 0x34
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#define ENABLE_VIDEO_MODE 0
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#define ENABLE_CMD_MODE BIT(0)
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#define DSI_VID_MODE_CFG 0x38
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-#define FRAME_BTA_ACK BIT(14)
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#define ENABLE_LOW_POWER (0x3f << 8)
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#define ENABLE_LOW_POWER_MASK (0x3f << 8)
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#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
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@@ -85,8 +89,13 @@
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#define VID_MODE_TYPE_MASK 0x3
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#define DSI_VID_PKT_SIZE 0x3c
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-#define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0)
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-#define VID_PKT_MAX_SIZE 0x3fff
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+#define VID_PKT_SIZE(p) ((p) & 0x3fff)
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+
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+#define DSI_VID_NUM_CHUNKS 0x40
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+#define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
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+
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+#define DSI_VID_NULL_SIZE 0x44
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+#define VID_NULL_SIZE(b) ((b) & 0x1fff)
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#define DSI_VID_HSA_TIME 0x48
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#define DSI_VID_HBP_TIME 0x4c
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@@ -95,6 +104,8 @@
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#define DSI_VID_VBP_LINES 0x58
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#define DSI_VID_VFP_LINES 0x5c
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#define DSI_VID_VACTIVE_LINES 0x60
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+#define DSI_EDPI_CMD_SIZE 0x64
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+
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#define DSI_CMD_MODE_CFG 0x68
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#define MAX_RD_PKT_SIZE_LP BIT(24)
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#define DCS_LW_TX_LP BIT(19)
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@@ -108,8 +119,8 @@
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#define GEN_SW_2P_TX_LP BIT(10)
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#define GEN_SW_1P_TX_LP BIT(9)
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#define GEN_SW_0P_TX_LP BIT(8)
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-#define EN_ACK_RQST BIT(1)
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-#define EN_TEAR_FX BIT(0)
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+#define ACK_RQST_EN BIT(1)
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+#define TEAR_FX_EN BIT(0)
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#define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
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DCS_LW_TX_LP | \
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@@ -125,27 +136,31 @@
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GEN_SW_0P_TX_LP)
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#define DSI_GEN_HDR 0x6c
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+/* TODO These 2 defines will be reworked thanks to mipi_dsi_create_packet() */
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#define GEN_HDATA(data) (((data) & 0xffff) << 8)
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-#define GEN_HDATA_MASK (0xffff << 8)
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#define GEN_HTYPE(type) (((type) & 0xff) << 0)
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-#define GEN_HTYPE_MASK 0xff
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#define DSI_GEN_PLD_DATA 0x70
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#define DSI_CMD_PKT_STATUS 0x74
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-#define GEN_CMD_EMPTY BIT(0)
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-#define GEN_CMD_FULL BIT(1)
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-#define GEN_PLD_W_EMPTY BIT(2)
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-#define GEN_PLD_W_FULL BIT(3)
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-#define GEN_PLD_R_EMPTY BIT(4)
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-#define GEN_PLD_R_FULL BIT(5)
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#define GEN_RD_CMD_BUSY BIT(6)
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+#define GEN_PLD_R_FULL BIT(5)
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+#define GEN_PLD_R_EMPTY BIT(4)
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+#define GEN_PLD_W_FULL BIT(3)
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+#define GEN_PLD_W_EMPTY BIT(2)
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+#define GEN_CMD_FULL BIT(1)
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+#define GEN_CMD_EMPTY BIT(0)
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#define DSI_TO_CNT_CFG 0x78
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#define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
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#define LPRX_TO_CNT(p) ((p) & 0xffff)
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+#define DSI_HS_RD_TO_CNT 0x7c
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+#define DSI_LP_RD_TO_CNT 0x80
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+#define DSI_HS_WR_TO_CNT 0x84
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+#define DSI_LP_WR_TO_CNT 0x88
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#define DSI_BTA_TO_CNT 0x8c
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+
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#define DSI_LPCLK_CTRL 0x94
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#define AUTO_CLKLANE_CTRL BIT(1)
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#define PHY_TXREQUESTCLKHS BIT(0)
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@@ -154,6 +169,7 @@
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#define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
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#define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
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+/* TODO Next register is slightly different between 1.30 & 1.31 IP version */
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#define DSI_PHY_TMR_CFG 0x9c
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#define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
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#define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
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@@ -170,12 +186,15 @@
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#define PHY_UNSHUTDOWNZ BIT(0)
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#define DSI_PHY_IF_CFG 0xa4
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-#define N_LANES(n) ((((n) - 1) & 0x3) << 0)
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#define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
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+#define N_LANES(n) (((n) - 1) & 0x3)
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+
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+#define DSI_PHY_ULPS_CTRL 0xa8
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+#define DSI_PHY_TX_TRIGGERS 0xac
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#define DSI_PHY_STATUS 0xb0
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-#define LOCK BIT(0)
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-#define STOP_STATE_CLK_LANE BIT(2)
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+#define PHY_STOP_STATE_CLK_LANE BIT(2)
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+#define PHY_LOCK BIT(0)
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#define DSI_PHY_TST_CTRL0 0xb4
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#define PHY_TESTCLK BIT(1)
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@@ -187,12 +206,13 @@
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#define PHY_TESTEN BIT(16)
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#define PHY_UNTESTEN 0
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#define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
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-#define PHY_TESTDIN(n) (((n) & 0xff) << 0)
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+#define PHY_TESTDIN(n) ((n) & 0xff)
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#define DSI_INT_ST0 0xbc
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#define DSI_INT_ST1 0xc0
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#define DSI_INT_MSK0 0xc4
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#define DSI_INT_MSK1 0xc8
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+#define DSI_PHY_TMR_RD_CFG 0xf4
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#define PHY_STATUS_TIMEOUT_US 10000
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#define CMD_PKT_STATUS_TIMEOUT_US 20000
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@@ -307,7 +327,7 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
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u32 val = 0;
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if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
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- val |= EN_ACK_RQST;
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+ val |= ACK_RQST_EN;
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if (lpm)
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val |= CMD_MODE_ALL_LP;
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@@ -506,8 +526,8 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
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* timeout clock division should be computed with the
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* high speed transmission counter timeout and byte lane...
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*/
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- dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
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- TX_ESC_CLK_DIVIDSION(esc_clk_division));
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+ dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
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+ TX_ESC_CLK_DIVISION(esc_clk_division));
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}
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static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
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@@ -520,7 +540,7 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
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color = DPI_COLOR_CODING_24BIT;
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break;
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case MIPI_DSI_FMT_RGB666:
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- color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
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+ color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
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break;
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case MIPI_DSI_FMT_RGB666_PACKED:
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color = DPI_COLOR_CODING_18BIT_1;
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@@ -535,7 +555,7 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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val |= HSYNC_ACTIVE_LOW;
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- dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
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+ dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
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dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
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dsi_write(dsi, DSI_DPI_CFG_POL, val);
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/*
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@@ -550,7 +570,7 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
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static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
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{
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- dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
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+ dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
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}
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static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
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@@ -571,7 +591,7 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
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/*
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* TODO dw drv improvements
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* compute high speed transmission counter timeout according
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- * to the timeout clock division (TO_CLK_DIVIDSION) and byte lane...
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+ * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
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*/
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dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
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/*
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@@ -684,13 +704,13 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
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dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
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PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
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- ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
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- val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
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+ ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
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+ val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
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if (ret < 0)
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DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
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ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
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- val, val & STOP_STATE_CLK_LANE, 1000,
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+ val, val & PHY_STOP_STATE_CLK_LANE, 1000,
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PHY_STATUS_TIMEOUT_US);
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if (ret < 0)
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DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
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Philippe CORNU