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@@ -83,7 +83,8 @@
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compatible = "mrvl,pxav3-mmc";
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reg = <0xab1000 0x200>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&chip CLKID_SDIO1XIN>;
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+ clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
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+ clock-names = "io", "core";
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status = "disabled";
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};
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@@ -348,36 +349,6 @@
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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};
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-
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- gpio4: gpio@5000 {
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- compatible = "snps,dw-apb-gpio";
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- reg = <0x5000 0x400>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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-
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- porte: gpio-port@4 {
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- compatible = "snps,dw-apb-gpio-port";
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- gpio-controller;
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- #gpio-cells = <2>;
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- snps,nr-gpios = <32>;
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- reg = <0>;
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- };
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- };
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-
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- gpio5: gpio@c000 {
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- compatible = "snps,dw-apb-gpio";
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- reg = <0xc000 0x400>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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-
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- portf: gpio-port@5 {
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- compatible = "snps,dw-apb-gpio-port";
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- gpio-controller;
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- #gpio-cells = <2>;
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- snps,nr-gpios = <32>;
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- reg = <0>;
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- };
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- };
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};
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chip: chip-control@ea0000 {
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@@ -466,6 +437,21 @@
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ranges = <0 0xfc0000 0x10000>;
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interrupt-parent = <&sic>;
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+ sm_gpio1: gpio@5000 {
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+ compatible = "snps,dw-apb-gpio";
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+ reg = <0x5000 0x400>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ portf: gpio-port@5 {
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+ compatible = "snps,dw-apb-gpio-port";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ snps,nr-gpios = <32>;
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+ reg = <0>;
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+ };
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+ };
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+
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i2c2: i2c@7000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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@@ -516,6 +502,21 @@
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status = "disabled";
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};
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+ sm_gpio0: gpio@c000 {
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+ compatible = "snps,dw-apb-gpio";
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+ reg = <0xc000 0x400>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ porte: gpio-port@4 {
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+ compatible = "snps,dw-apb-gpio-port";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ snps,nr-gpios = <32>;
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+ reg = <0>;
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+ };
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+ };
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+
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sysctrl: pin-controller@d000 {
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compatible = "marvell,berlin2q-system-ctrl";
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reg = <0xd000 0x100>;
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