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@@ -114,7 +114,6 @@ struct fimd_context {
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struct fimd_win_data win_data[WINDOWS_NR];
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unsigned int default_win;
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unsigned long irq_flags;
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- u32 vidcon0;
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u32 vidcon1;
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bool suspended;
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int pipe;
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@@ -266,26 +265,19 @@ static void fimd_commit(struct exynos_drm_manager *mgr)
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VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
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writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
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- /* setup clock source, clock divider, enable dma. */
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- val = ctx->vidcon0;
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- val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
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+ /*
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+ * fields of register with prefix '_F' would be updated
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+ * at vsync(same as dma start)
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+ */
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+ val = VIDCON0_ENVID | VIDCON0_ENVID_F;
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- if (ctx->driver_data->has_clksel) {
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- val &= ~VIDCON0_CLKSEL_MASK;
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+ if (ctx->driver_data->has_clksel)
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val |= VIDCON0_CLKSEL_LCD;
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- }
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clkdiv = fimd_calc_clkdiv(ctx, mode);
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if (clkdiv > 1)
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val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
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- else
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- val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
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- /*
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- * fields of register with prefix '_F' would be updated
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- * at vsync(same as dma start)
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- */
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- val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
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writel(val, ctx->regs + VIDCON0);
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}
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