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@@ -73,7 +73,7 @@
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#define MTK_SPI_IDLE 0
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#define MTK_SPI_PAUSED 1
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-#define MTK_SPI_MAX_FIFO_SIZE 32
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+#define MTK_SPI_MAX_FIFO_SIZE 32U
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#define MTK_SPI_PACKET_SIZE 1024
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struct mtk_spi_compatible {
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@@ -333,7 +333,7 @@ static int mtk_spi_fifo_transfer(struct spi_master *master,
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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mdata->cur_transfer = xfer;
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- mdata->xfer_len = xfer->len;
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+ mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
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mtk_spi_prepare_transfer(master, xfer);
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mtk_spi_setup_packet(master);
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@@ -410,7 +410,10 @@ static bool mtk_spi_can_dma(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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- return xfer->len > MTK_SPI_MAX_FIFO_SIZE;
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+ /* Buffers for DMA transactions must be 4-byte aligned */
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+ return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
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+ (unsigned long)xfer->tx_buf % 4 == 0 &&
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+ (unsigned long)xfer->rx_buf % 4 == 0);
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}
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static int mtk_spi_setup(struct spi_device *spi)
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@@ -451,7 +454,33 @@ static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
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®_val, remainder);
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}
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}
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- spi_finalize_current_transfer(master);
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+
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+ trans->len -= mdata->xfer_len;
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+ if (!trans->len) {
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+ spi_finalize_current_transfer(master);
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+ return IRQ_HANDLED;
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+ }
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+
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+ if (trans->tx_buf)
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+ trans->tx_buf += mdata->xfer_len;
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+ if (trans->rx_buf)
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+ trans->rx_buf += mdata->xfer_len;
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+
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+ mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, trans->len);
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+ mtk_spi_setup_packet(master);
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+
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+ cnt = trans->len / 4;
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+ iowrite32_rep(mdata->base + SPI_TX_DATA_REG, trans->tx_buf, cnt);
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+
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+ remainder = trans->len % 4;
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+ if (remainder > 0) {
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+ reg_val = 0;
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+ memcpy(®_val, trans->tx_buf + (cnt * 4), remainder);
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+ writel(reg_val, mdata->base + SPI_TX_DATA_REG);
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+ }
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+
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+ mtk_spi_enable_transfer(master);
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+
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return IRQ_HANDLED;
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}
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