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@@ -59,6 +59,8 @@
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serial1 = &uart3;
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tcb0 = &tcb0;
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tcb1 = &tcb1;
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+ i2s0 = &i2s0;
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+ i2s1 = &i2s1;
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};
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cpus {
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@@ -1314,6 +1316,24 @@
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clocks = <&clk32k>;
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};
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+ i2s0: i2s@f8050000 {
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+ compatible = "atmel,sama5d2-i2s";
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+ reg = <0xf8050000 0x100>;
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+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
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+ dmas = <&dma0
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+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
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+ AT91_XDMAC_DT_PERID(31))>,
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+ <&dma0
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+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
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+ AT91_XDMAC_DT_PERID(32))>;
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+ dma-names = "tx", "rx";
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+ clocks = <&i2s0_clk>, <&i2s0_gclk>;
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+ clock-names = "pclk", "gclk";
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+ assigned-clocks = <&i2s0muxck>;
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+ assigned-clock-parents = <&i2s0_gclk>;
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+ status = "disabled";
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+ };
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+
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can0: can@f8054000 {
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compatible = "bosch,m_can";
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reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
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@@ -1518,6 +1538,24 @@
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status = "disabled";
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};
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+ i2s1: i2s@fc04c000 {
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+ compatible = "atmel,sama5d2-i2s";
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+ reg = <0xfc04c000 0x100>;
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+ interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
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+ dmas = <&dma0
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+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
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+ AT91_XDMAC_DT_PERID(33))>,
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+ <&dma0
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+ (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
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+ AT91_XDMAC_DT_PERID(34))>;
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+ dma-names = "tx", "rx";
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+ clocks = <&i2s1_clk>, <&i2s1_gclk>;
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+ clock-names = "pclk", "gclk";
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+ assigned-clocks = <&i2s1muxck>;
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+ assigned-parrents = <&i2s1_gclk>;
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+ status = "disabled";
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+ };
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+
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can1: can@fc050000 {
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compatible = "bosch,m_can";
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reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
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