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@@ -1282,7 +1282,7 @@ static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
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if (!pi->sclk_dpm_key_disabled) {
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PPSMC_Result smc_result =
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- ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, n);
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+ ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
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if (smc_result != PPSMC_Result_OK)
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return -EINVAL;
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}
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@@ -1296,7 +1296,7 @@ static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
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if (!pi->mclk_dpm_key_disabled) {
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PPSMC_Result smc_result =
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- ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_ForceState, n);
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+ ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
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if (smc_result != PPSMC_Result_OK)
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return -EINVAL;
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}
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@@ -3736,7 +3736,6 @@ int ci_dpm_force_performance_level(struct radeon_device *rdev,
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enum radeon_dpm_forced_level level)
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{
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struct ci_power_info *pi = ci_get_pi(rdev);
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- PPSMC_Result smc_result;
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u32 tmp, levels, i;
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int ret;
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@@ -3845,21 +3844,9 @@ int ci_dpm_force_performance_level(struct radeon_device *rdev,
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}
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}
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} else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
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- if (!pi->sclk_dpm_key_disabled) {
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- smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel);
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- if (smc_result != PPSMC_Result_OK)
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- return -EINVAL;
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- }
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- if (!pi->mclk_dpm_key_disabled) {
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- smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_NoForcedLevel);
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- if (smc_result != PPSMC_Result_OK)
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- return -EINVAL;
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- }
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- if (!pi->pcie_dpm_key_disabled) {
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- smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_UnForceLevel);
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- if (smc_result != PPSMC_Result_OK)
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- return -EINVAL;
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- }
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+ ret = ci_upload_dpm_level_enable_mask(rdev);
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+ if (ret)
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+ return ret;
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}
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rdev->pm.dpm.forced_level = level;
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