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@@ -163,6 +163,7 @@
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<0 29 IRQ_TYPE_LEVEL_HIGH>,
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<0 30 IRQ_TYPE_LEVEL_HIGH>,
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<0 31 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
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power-domains = <&pd_c4>;
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};
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@@ -197,6 +198,7 @@
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<0 55 IRQ_TYPE_LEVEL_HIGH>,
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<0 56 IRQ_TYPE_LEVEL_HIGH>,
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<0 57 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
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power-domains = <&pd_c4>;
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};
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@@ -724,15 +726,16 @@
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mstp4_clks: mstp4_clks@e6150140 {
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compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
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- clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
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+ clocks = <&main_div2_clk>, <&main_div2_clk>,
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+ <&cpg_clocks R8A73A4_CLK_HP>,
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<&cpg_clocks R8A73A4_CLK_HP>;
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#clock-cells = <1>;
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clock-indices = <
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- R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
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- R8A73A4_CLK_IIC3
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+ R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5
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+ R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3
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>;
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clock-output-names =
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- "iic5", "iic4", "iic3";
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+ "irqc", "iic5", "iic4", "iic3";
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};
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mstp5_clks: mstp5_clks@e6150144 {
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compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
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