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@@ -438,6 +438,39 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
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}
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}
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EXPORT_SYMBOL(drm_dp_link_configure);
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EXPORT_SYMBOL(drm_dp_link_configure);
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+/**
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+ * drm_dp_downstream_max_clock() - extract branch device max
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+ * pixel rate for legacy VGA
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+ * converter or max TMDS clock
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+ * rate for others
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+ * @dpcd: DisplayPort configuration data
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+ * @port_cap: port capabilities
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+ *
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+ * Returns max clock in kHz on success or 0 if max clock not defined
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+ */
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+int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
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+ const u8 port_cap[4])
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+{
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+ int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
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+ bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
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+ DP_DETAILED_CAP_INFO_AVAILABLE;
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+
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+ if (!detailed_cap_info)
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+ return 0;
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+
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+ switch (type) {
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+ case DP_DS_PORT_TYPE_VGA:
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+ return port_cap[1] * 8 * 1000;
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+ case DP_DS_PORT_TYPE_DVI:
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+ case DP_DS_PORT_TYPE_HDMI:
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+ case DP_DS_PORT_TYPE_DP_DUALMODE:
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+ return port_cap[1] * 2500;
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+ default:
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+ return 0;
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+ }
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+}
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+EXPORT_SYMBOL(drm_dp_downstream_max_clock);
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+
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/*
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/*
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* I2C-over-AUX implementation
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* I2C-over-AUX implementation
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*/
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*/
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