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@@ -4919,12 +4919,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
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intel_ddi_enable_pipe_clock(intel_crtc);
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- if (INTEL_INFO(dev)->gen == 9)
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+ if (INTEL_INFO(dev)->gen >= 9)
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skylake_pfit_enable(intel_crtc);
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- else if (INTEL_INFO(dev)->gen < 9)
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- ironlake_pfit_enable(intel_crtc);
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else
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- MISSING_CASE(INTEL_INFO(dev)->gen);
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+ ironlake_pfit_enable(intel_crtc);
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/*
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* On ILK+ LUT must be loaded before the pipe is running but with
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@@ -5056,12 +5054,10 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
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intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
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- if (INTEL_INFO(dev)->gen == 9)
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+ if (INTEL_INFO(dev)->gen >= 9)
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skylake_scaler_disable(intel_crtc);
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- else if (INTEL_INFO(dev)->gen < 9)
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- ironlake_pfit_disable(intel_crtc);
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else
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- MISSING_CASE(INTEL_INFO(dev)->gen);
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+ ironlake_pfit_disable(intel_crtc);
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intel_ddi_disable_pipe_clock(intel_crtc);
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@@ -9784,12 +9780,10 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
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}
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if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
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- if (INTEL_INFO(dev)->gen == 9)
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+ if (INTEL_INFO(dev)->gen >= 9)
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skylake_get_pfit_config(crtc, pipe_config);
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- else if (INTEL_INFO(dev)->gen < 9)
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- ironlake_get_pfit_config(crtc, pipe_config);
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else
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- MISSING_CASE(INTEL_INFO(dev)->gen);
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+ ironlake_get_pfit_config(crtc, pipe_config);
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}
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if (IS_HASWELL(dev))
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