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@@ -10,35 +10,22 @@
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* (at your option) any later version.
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*/
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-#include <linux/gpio.h>
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-#include <linux/suspend.h>
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-#include <linux/sched.h>
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-#include <linux/proc_fs.h>
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#include <linux/genalloc.h>
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-#include <linux/interrupt.h>
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-#include <linux/sysfs.h>
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-#include <linux/module.h>
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+#include <linux/io.h>
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+#include <linux/of_address.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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-#include <linux/of_address.h>
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-#include <linux/platform_device.h>
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-#include <linux/platform_data/atmel.h>
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-#include <linux/io.h>
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+#include <linux/suspend.h>
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+
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#include <linux/clk/at91_pmc.h>
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-#include <asm/irq.h>
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-#include <linux/atomic.h>
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-#include <asm/mach/time.h>
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-#include <asm/mach/irq.h>
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-#include <asm/fncpy.h>
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#include <asm/cacheflush.h>
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+#include <asm/fncpy.h>
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#include <asm/system_misc.h>
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#include "generic.h"
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#include "pm.h"
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-static void __iomem *pmc;
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-
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/*
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* FIXME: this is needed to communicate between the pinctrl driver and
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* the PM implementation in the machine. Possibly part of the PM
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@@ -50,12 +37,13 @@ extern void at91_pinctrl_gpio_suspend(void);
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extern void at91_pinctrl_gpio_resume(void);
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#endif
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-static struct {
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- unsigned long uhp_udp_mask;
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- int memctrl;
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-} at91_pm_data;
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+static struct at91_pm_data pm_data;
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-static void __iomem *at91_ramc_base[2];
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+#define at91_ramc_read(id, field) \
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+ __raw_readl(pm_data.ramc[id] + field)
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+
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+#define at91_ramc_write(id, field, value) \
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+ __raw_writel(value, pm_data.ramc[id] + field)
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static int at91_pm_valid_state(suspend_state_t state)
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{
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@@ -91,10 +79,10 @@ static int at91_pm_verify_clocks(void)
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unsigned long scsr;
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int i;
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- scsr = readl(pmc + AT91_PMC_SCSR);
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+ scsr = readl(pm_data.pmc + AT91_PMC_SCSR);
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/* USB must not be using PLLB */
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- if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
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+ if ((scsr & pm_data.uhp_udp_mask) != 0) {
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pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
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return 0;
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}
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@@ -105,7 +93,7 @@ static int at91_pm_verify_clocks(void)
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if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
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continue;
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- css = readl(pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
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+ css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
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if (css != AT91_PMC_CSS_SLOW) {
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pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
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return 0;
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@@ -131,25 +119,18 @@ int at91_suspend_entering_slow_clock(void)
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}
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EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
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-static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
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- void __iomem *ramc1, int memctrl);
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-
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-extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
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- void __iomem *ramc1, int memctrl);
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+static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
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+extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
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extern u32 at91_pm_suspend_in_sram_sz;
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static void at91_pm_suspend(suspend_state_t state)
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{
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- unsigned int pm_data = at91_pm_data.memctrl;
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-
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- pm_data |= (state == PM_SUSPEND_MEM) ?
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- AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
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+ pm_data.mode = (state == PM_SUSPEND_MEM) ? AT91_PM_SLOW_CLOCK : 0;
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flush_cache_all();
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outer_disable();
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- at91_suspend_sram_fn(pmc, at91_ramc_base[0],
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- at91_ramc_base[1], pm_data);
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+ at91_suspend_sram_fn(&pm_data);
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outer_resume();
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}
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@@ -224,12 +205,6 @@ static struct platform_device at91_cpuidle_device = {
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.name = "cpuidle-at91",
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};
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-static void at91_pm_set_standby(void (*at91_standby)(void))
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-{
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- if (at91_standby)
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- at91_cpuidle_device.dev.platform_data = at91_standby;
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-}
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-
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/*
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* The AT91RM9200 goes into self-refresh mode with this command, and will
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* terminate self-refresh automatically on the next SDRAM access.
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@@ -241,20 +216,15 @@ static void at91_pm_set_standby(void (*at91_standby)(void))
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*/
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static void at91rm9200_standby(void)
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{
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- u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
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-
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asm volatile(
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"b 1f\n\t"
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".align 5\n\t"
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"1: mcr p15, 0, %0, c7, c10, 4\n\t"
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- " str %0, [%1, %2]\n\t"
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- " str %3, [%1, %4]\n\t"
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+ " str %2, [%1, %3]\n\t"
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" mcr p15, 0, %0, c7, c0, 4\n\t"
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- " str %5, [%1, %2]"
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:
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- : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
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- "r" (1), "r" (AT91_MC_SDRAMC_SRR),
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- "r" (lpr));
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+ : "r" (0), "r" (pm_data.ramc[0]),
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+ "r" (1), "r" (AT91_MC_SDRAMC_SRR));
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}
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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@@ -265,12 +235,27 @@ static void at91_ddr_standby(void)
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/* Those two values allow us to delay self-refresh activation
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* to the maximum. */
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u32 lpr0, lpr1 = 0;
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+ u32 mdr, saved_mdr0, saved_mdr1 = 0;
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u32 saved_lpr0, saved_lpr1 = 0;
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- if (at91_ramc_base[1]) {
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+ /* LPDDR1 --> force DDR2 mode during self-refresh */
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+ saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
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+ if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
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+ mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
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+ mdr |= AT91_DDRSDRC_MD_DDR2;
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+ at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
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+ }
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+
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+ if (pm_data.ramc[1]) {
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saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
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lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
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lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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+ saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
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+ if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
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+ mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
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+ mdr |= AT91_DDRSDRC_MD_DDR2;
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+ at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
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+ }
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}
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saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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@@ -279,14 +264,33 @@ static void at91_ddr_standby(void)
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/* self-refresh mode now */
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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- if (at91_ramc_base[1])
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+ if (pm_data.ramc[1])
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at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
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cpu_do_idle();
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+ at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
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at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
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- if (at91_ramc_base[1])
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+ if (pm_data.ramc[1]) {
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+ at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
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+ }
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+}
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+
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+static void sama5d3_ddr_standby(void)
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+{
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+ u32 lpr0;
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+ u32 saved_lpr0;
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+
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+ saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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+ lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
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+ lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
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+
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+ at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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+
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+ cpu_do_idle();
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+
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+ at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
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}
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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@@ -297,7 +301,7 @@ static void at91sam9_sdram_standby(void)
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u32 lpr0, lpr1 = 0;
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u32 saved_lpr0, saved_lpr1 = 0;
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- if (at91_ramc_base[1]) {
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+ if (pm_data.ramc[1]) {
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saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
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lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
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lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
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@@ -309,21 +313,33 @@ static void at91sam9_sdram_standby(void)
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/* self-refresh mode now */
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at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
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- if (at91_ramc_base[1])
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+ if (pm_data.ramc[1])
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at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
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cpu_do_idle();
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at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
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- if (at91_ramc_base[1])
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+ if (pm_data.ramc[1])
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at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
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}
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+struct ramc_info {
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+ void (*idle)(void);
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+ unsigned int memctrl;
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+};
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+
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+static const struct ramc_info ramc_infos[] __initconst = {
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+ { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
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+ { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
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+ { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
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+ { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
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+};
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+
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static const struct of_device_id const ramc_ids[] __initconst = {
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- { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
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- { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
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- { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
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- { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
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+ { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
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+ { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
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+ { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
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+ { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
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{ /*sentinel*/ }
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};
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@@ -332,15 +348,18 @@ static __init void at91_dt_ramc(void)
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struct device_node *np;
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const struct of_device_id *of_id;
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int idx = 0;
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- const void *standby = NULL;
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+ void *standby = NULL;
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+ const struct ramc_info *ramc;
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for_each_matching_node_and_match(np, ramc_ids, &of_id) {
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- at91_ramc_base[idx] = of_iomap(np, 0);
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- if (!at91_ramc_base[idx])
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+ pm_data.ramc[idx] = of_iomap(np, 0);
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+ if (!pm_data.ramc[idx])
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panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
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+ ramc = of_id->data;
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if (!standby)
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- standby = of_id->data;
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+ standby = ramc->idle;
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+ pm_data.memctrl = ramc->memctrl;
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idx++;
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}
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@@ -353,7 +372,7 @@ static __init void at91_dt_ramc(void)
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return;
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}
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- at91_pm_set_standby(standby);
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+ at91_cpuidle_device.dev.platform_data = standby;
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}
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static void at91rm9200_idle(void)
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@@ -362,12 +381,12 @@ static void at91rm9200_idle(void)
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* Disable the processor clock. The processor will be automatically
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* re-enabled by an interrupt or by a reset.
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*/
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- writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
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+ writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
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}
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static void at91sam9_idle(void)
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{
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- writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
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+ writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
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cpu_do_idle();
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}
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@@ -417,31 +436,46 @@ static void __init at91_pm_sram_init(void)
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&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
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}
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+struct pmc_info {
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+ unsigned long uhp_udp_mask;
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+};
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+
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+static const struct pmc_info pmc_infos[] __initconst = {
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+ { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP },
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+ { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP },
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+ { .uhp_udp_mask = AT91SAM926x_PMC_UHP },
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+};
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+
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static const struct of_device_id atmel_pmc_ids[] __initconst = {
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- { .compatible = "atmel,at91rm9200-pmc" },
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- { .compatible = "atmel,at91sam9260-pmc" },
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- { .compatible = "atmel,at91sam9g45-pmc" },
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- { .compatible = "atmel,at91sam9n12-pmc" },
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- { .compatible = "atmel,at91sam9x5-pmc" },
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- { .compatible = "atmel,sama5d3-pmc" },
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- { .compatible = "atmel,sama5d2-pmc" },
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+ { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
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+ { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
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+ { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
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+ { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
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+ { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
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+ { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
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+ { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
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{ /* sentinel */ },
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};
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static void __init at91_pm_init(void (*pm_idle)(void))
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{
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struct device_node *pmc_np;
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+ const struct of_device_id *of_id;
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+ const struct pmc_info *pmc;
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|
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if (at91_cpuidle_device.dev.platform_data)
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platform_device_register(&at91_cpuidle_device);
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|
|
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- pmc_np = of_find_matching_node(NULL, atmel_pmc_ids);
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- pmc = of_iomap(pmc_np, 0);
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- if (!pmc) {
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+ pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
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|
+ pm_data.pmc = of_iomap(pmc_np, 0);
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|
|
+ if (!pm_data.pmc) {
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|
pr_err("AT91: PM not supported, PMC not found\n");
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return;
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}
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|
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+ pmc = of_id->data;
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+ pm_data.uhp_udp_mask = pmc->uhp_udp_mask;
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|
+
|
|
|
if (pm_idle)
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|
arm_pm_idle = pm_idle;
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|
|
|
|
|
@@ -462,40 +496,17 @@ void __init at91rm9200_pm_init(void)
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|
*/
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at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
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|
|
|
|
- at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
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|
- at91_pm_data.memctrl = AT91_MEMCTRL_MC;
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|
|
-
|
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at91_pm_init(at91rm9200_idle);
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|
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}
|
|
|
|
|
|
-void __init at91sam9260_pm_init(void)
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|
-{
|
|
|
- at91_dt_ramc();
|
|
|
- at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
|
|
|
- at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
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|
|
- at91_pm_init(at91sam9_idle);
|
|
|
-}
|
|
|
-
|
|
|
-void __init at91sam9g45_pm_init(void)
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|
-{
|
|
|
- at91_dt_ramc();
|
|
|
- at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
|
|
|
- at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
|
|
|
- at91_pm_init(at91sam9_idle);
|
|
|
-}
|
|
|
-
|
|
|
-void __init at91sam9x5_pm_init(void)
|
|
|
+void __init at91sam9_pm_init(void)
|
|
|
{
|
|
|
at91_dt_ramc();
|
|
|
- at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
|
|
|
- at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
|
|
|
at91_pm_init(at91sam9_idle);
|
|
|
}
|
|
|
|
|
|
void __init sama5_pm_init(void)
|
|
|
{
|
|
|
at91_dt_ramc();
|
|
|
- at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
|
|
|
- at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
|
|
|
at91_pm_init(NULL);
|
|
|
}
|
Olof Johansson