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@@ -55,12 +55,10 @@ static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
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struct intel_crtc_state *config,
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int target_dsi_clk)
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{
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- unsigned int calc_m = 0, calc_p = 0;
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unsigned int m_min, m_max, p_min = 2, p_max = 6;
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unsigned int m, n, p;
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- int ref_clk;
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- int delta = target_dsi_clk;
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- u32 m_seed;
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+ unsigned int calc_m, calc_p;
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+ int delta, ref_clk;
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/* target_dsi_clk is expected in kHz */
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if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) {
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@@ -80,6 +78,10 @@ static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
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m_max = 92;
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}
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+ calc_p = p_min;
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+ calc_m = m_min;
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+ delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n));
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+
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for (m = m_min; m <= m_max && delta; m++) {
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for (p = p_min; p <= p_max && delta; p++) {
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/*
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@@ -97,11 +99,10 @@ static int dsi_calc_mnp(struct drm_i915_private *dev_priv,
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}
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/* register has log2(N1), this works fine for powers of two */
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- n = ffs(n) - 1;
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- m_seed = lfsr_converts[calc_m - 62];
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config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
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- config->dsi_pll.div = n << DSI_PLL_N1_DIV_SHIFT |
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- m_seed << DSI_PLL_M1_DIV_SHIFT;
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+ config->dsi_pll.div =
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+ (ffs(n) - 1) << DSI_PLL_N1_DIV_SHIFT |
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+ (u32)lfsr_converts[calc_m - 62] << DSI_PLL_M1_DIV_SHIFT;
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return 0;
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}
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