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@@ -363,6 +363,17 @@ static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_
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static struct clk_onecell_data clk_data;
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+static struct clk ** const uart_clks[] __initconst = {
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+ &clks[IMX7D_UART1_ROOT_CLK],
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+ &clks[IMX7D_UART2_ROOT_CLK],
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+ &clks[IMX7D_UART3_ROOT_CLK],
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+ &clks[IMX7D_UART4_ROOT_CLK],
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+ &clks[IMX7D_UART5_ROOT_CLK],
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+ &clks[IMX7D_UART6_ROOT_CLK],
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+ &clks[IMX7D_UART7_ROOT_CLK],
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+ NULL
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+};
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+
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static void __init imx7d_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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@@ -856,5 +867,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
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/* set uart module clock's parent clock source that must be great then 80MHz */
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clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
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+ imx_register_uart_clocks(uart_clks);
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+
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}
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CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);
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