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@@ -47,6 +47,7 @@ struct vf610_mscm_ir_chip_data {
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void __iomem *mscm_ir_base;
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u16 cpu_mask;
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u16 saved_irsprc[MSCM_IRSPRC_NUM];
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+ bool is_nvic;
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};
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static struct vf610_mscm_ir_chip_data *mscm_ir_data;
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@@ -101,7 +102,7 @@ static void vf610_mscm_ir_enable(struct irq_data *data)
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writew_relaxed(chip_data->cpu_mask,
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chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
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- irq_chip_unmask_parent(data);
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+ irq_chip_enable_parent(data);
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}
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static void vf610_mscm_ir_disable(struct irq_data *data)
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@@ -111,7 +112,7 @@ static void vf610_mscm_ir_disable(struct irq_data *data)
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writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
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- irq_chip_mask_parent(data);
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+ irq_chip_disable_parent(data);
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}
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static struct irq_chip vf610_mscm_ir_irq_chip = {
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@@ -143,10 +144,17 @@ static int vf610_mscm_ir_domain_alloc(struct irq_domain *domain, unsigned int vi
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domain->host_data);
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gic_data.np = domain->parent->of_node;
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- gic_data.args_count = 3;
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- gic_data.args[0] = GIC_SPI;
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- gic_data.args[1] = irq_data->args[0];
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- gic_data.args[2] = irq_data->args[1];
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+
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+ if (mscm_ir_data->is_nvic) {
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+ gic_data.args_count = 1;
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+ gic_data.args[0] = irq_data->args[0];
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+ } else {
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+ gic_data.args_count = 3;
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+ gic_data.args[0] = GIC_SPI;
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+ gic_data.args[1] = irq_data->args[0];
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+ gic_data.args[2] = irq_data->args[1];
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+ }
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+
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
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}
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@@ -199,6 +207,9 @@ static int __init vf610_mscm_ir_of_init(struct device_node *node,
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goto out_unmap;
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}
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+ if (of_device_is_compatible(domain->parent->of_node, "arm,armv7m-nvic"))
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+ mscm_ir_data->is_nvic = true;
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+
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cpu_pm_register_notifier(&mscm_ir_notifier_block);
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return 0;
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