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@@ -57,8 +57,11 @@ struct iommu_domain {
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struct iommu_domain_geometry geometry;
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};
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-#define IOMMU_CAP_CACHE_COHERENCY 0x1
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-#define IOMMU_CAP_INTR_REMAP 0x2 /* isolates device intrs */
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+enum iommu_cap {
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+ IOMMU_CAP_CACHE_COHERENCY, /* IOMMU can enforce cache coherent DMA
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+ transactions */
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+ IOMMU_CAP_INTR_REMAP, /* IOMMU supports interrupt isolation */
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+};
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/*
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* Following constraints are specifc to FSL_PAMUV1:
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@@ -155,7 +158,7 @@ extern size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova,
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size_t size);
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extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova);
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extern int iommu_domain_has_cap(struct iommu_domain *domain,
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- unsigned long cap);
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+ enum iommu_cap cap);
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extern void iommu_set_fault_handler(struct iommu_domain *domain,
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iommu_fault_handler_t handler, void *token);
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@@ -305,7 +308,7 @@ static inline phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_ad
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}
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static inline int iommu_domain_has_cap(struct iommu_domain *domain,
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- unsigned long cap)
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+ enum iommu_cap cap)
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{
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return 0;
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}
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