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@@ -551,8 +551,8 @@ static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
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}
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static int intel_suspend_complete(struct drm_i915_private *dev_priv);
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-static int intel_resume_prepare(struct drm_i915_private *dev_priv,
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- bool rpm_resume);
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+static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
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+ bool rpm_resume);
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static int i915_drm_suspend(struct drm_device *dev)
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{
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@@ -744,7 +744,7 @@ static int i915_drm_resume(struct drm_device *dev)
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static int i915_drm_resume_early(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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- int ret;
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+ int ret = 0;
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/*
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* We have a resume ordering issue with the snd-hda driver also
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@@ -760,7 +760,10 @@ static int i915_drm_resume_early(struct drm_device *dev)
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pci_set_master(dev->pdev);
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- ret = intel_resume_prepare(dev_priv, false);
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+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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+ hsw_disable_pc8(dev_priv);
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+ else if (IS_VALLEYVIEW(dev_priv))
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+ ret = vlv_resume_prepare(dev_priv, false);
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if (ret)
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DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret);
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@@ -986,25 +989,6 @@ static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
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return 0;
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}
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-static int snb_resume_prepare(struct drm_i915_private *dev_priv,
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- bool rpm_resume)
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-{
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- struct drm_device *dev = dev_priv->dev;
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-
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- if (rpm_resume)
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- intel_init_pch_refclk(dev);
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-
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- return 0;
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-}
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-
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-static int hsw_resume_prepare(struct drm_i915_private *dev_priv,
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- bool rpm_resume)
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-{
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- hsw_disable_pc8(dev_priv);
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-
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- return 0;
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-}
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-
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/*
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* Save all Gunit registers that may be lost after a D3 and a subsequent
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* S0i[R123] transition. The list of registers needing a save/restore is
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@@ -1462,7 +1446,7 @@ static int intel_runtime_resume(struct device *device)
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struct pci_dev *pdev = to_pci_dev(device);
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struct drm_device *dev = pci_get_drvdata(pdev);
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struct drm_i915_private *dev_priv = dev->dev_private;
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- int ret;
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+ int ret = 0;
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if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
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return -ENODEV;
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@@ -1472,7 +1456,13 @@ static int intel_runtime_resume(struct device *device)
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intel_opregion_notify_adapter(dev, PCI_D0);
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dev_priv->pm.suspended = false;
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- ret = intel_resume_prepare(dev_priv, true);
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+ if (IS_GEN6(dev_priv))
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+ intel_init_pch_refclk(dev);
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+ else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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+ hsw_disable_pc8(dev_priv);
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+ else if (IS_VALLEYVIEW(dev_priv))
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+ ret = vlv_resume_prepare(dev_priv, true);
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+
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/*
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* No point of rolling back things in case of an error, as the best
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* we can do is to hope that things will still work (and disable RPM).
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@@ -1510,29 +1500,6 @@ static int intel_suspend_complete(struct drm_i915_private *dev_priv)
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return ret;
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}
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-/*
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- * This function implements common functionality of runtime and system
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- * resume sequence. Variable rpm_resume used for implementing different
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- * code paths.
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- */
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-static int intel_resume_prepare(struct drm_i915_private *dev_priv,
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- bool rpm_resume)
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-{
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- struct drm_device *dev = dev_priv->dev;
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- int ret;
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-
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- if (IS_GEN6(dev))
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- ret = snb_resume_prepare(dev_priv, rpm_resume);
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- else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
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- ret = hsw_resume_prepare(dev_priv, rpm_resume);
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- else if (IS_VALLEYVIEW(dev))
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- ret = vlv_resume_prepare(dev_priv, rpm_resume);
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- else
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- ret = 0;
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-
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- return ret;
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-}
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-
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static const struct dev_pm_ops i915_pm_ops = {
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/*
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* S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
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