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@@ -4789,7 +4789,7 @@ restart_ih:
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wake_up(&rdev->irq.vblank_queue);
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}
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if (atomic_read(&rdev->irq.pflip[0]))
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- radeon_crtc_handle_flip(rdev, 0);
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+ radeon_crtc_handle_vblank(rdev, 0);
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rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
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DRM_DEBUG("IH: D1 vblank\n");
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}
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@@ -4815,7 +4815,7 @@ restart_ih:
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wake_up(&rdev->irq.vblank_queue);
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}
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if (atomic_read(&rdev->irq.pflip[1]))
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- radeon_crtc_handle_flip(rdev, 1);
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+ radeon_crtc_handle_vblank(rdev, 1);
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rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
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DRM_DEBUG("IH: D2 vblank\n");
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}
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@@ -4841,7 +4841,7 @@ restart_ih:
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wake_up(&rdev->irq.vblank_queue);
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}
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if (atomic_read(&rdev->irq.pflip[2]))
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- radeon_crtc_handle_flip(rdev, 2);
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+ radeon_crtc_handle_vblank(rdev, 2);
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rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
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DRM_DEBUG("IH: D3 vblank\n");
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}
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@@ -4867,7 +4867,7 @@ restart_ih:
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wake_up(&rdev->irq.vblank_queue);
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}
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if (atomic_read(&rdev->irq.pflip[3]))
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- radeon_crtc_handle_flip(rdev, 3);
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+ radeon_crtc_handle_vblank(rdev, 3);
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rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
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DRM_DEBUG("IH: D4 vblank\n");
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}
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@@ -4893,7 +4893,7 @@ restart_ih:
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wake_up(&rdev->irq.vblank_queue);
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}
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if (atomic_read(&rdev->irq.pflip[4]))
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- radeon_crtc_handle_flip(rdev, 4);
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+ radeon_crtc_handle_vblank(rdev, 4);
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rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
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DRM_DEBUG("IH: D5 vblank\n");
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}
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@@ -4919,7 +4919,7 @@ restart_ih:
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wake_up(&rdev->irq.vblank_queue);
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}
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if (atomic_read(&rdev->irq.pflip[5]))
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- radeon_crtc_handle_flip(rdev, 5);
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+ radeon_crtc_handle_vblank(rdev, 5);
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rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
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DRM_DEBUG("IH: D6 vblank\n");
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}
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