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@@ -79,7 +79,7 @@ static void setChipClock(unsigned int frequency)
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static void setMemoryClock(unsigned int frequency)
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{
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- unsigned int ulReg, divisor;
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+ unsigned int reg, divisor;
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/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
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if (getChipType() == SM750LE)
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@@ -95,24 +95,24 @@ static void setMemoryClock(unsigned int frequency)
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divisor = roundedDiv(get_mxclk_freq(), frequency);
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/* Set the corresponding divisor in the register. */
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- ulReg = PEEK32(CURRENT_GATE);
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+ reg = PEEK32(CURRENT_GATE);
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switch (divisor) {
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default:
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case 1:
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- ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_1);
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+ reg = FIELD_SET(reg, CURRENT_GATE, M2XCLK, DIV_1);
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break;
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case 2:
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- ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_2);
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+ reg = FIELD_SET(reg, CURRENT_GATE, M2XCLK, DIV_2);
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break;
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case 3:
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- ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_3);
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+ reg = FIELD_SET(reg, CURRENT_GATE, M2XCLK, DIV_3);
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break;
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case 4:
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- ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_4);
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+ reg = FIELD_SET(reg, CURRENT_GATE, M2XCLK, DIV_4);
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break;
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}
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- setCurrentGate(ulReg);
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+ setCurrentGate(reg);
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}
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}
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@@ -126,7 +126,7 @@ static void setMemoryClock(unsigned int frequency)
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*/
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static void setMasterClock(unsigned int frequency)
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{
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- unsigned int ulReg, divisor;
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+ unsigned int reg, divisor;
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/* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
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if (getChipType() == SM750LE)
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@@ -142,24 +142,24 @@ static void setMasterClock(unsigned int frequency)
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divisor = roundedDiv(get_mxclk_freq(), frequency);
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/* Set the corresponding divisor in the register. */
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- ulReg = PEEK32(CURRENT_GATE);
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+ reg = PEEK32(CURRENT_GATE);
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switch (divisor) {
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default:
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case 3:
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- ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_3);
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+ reg = FIELD_SET(reg, CURRENT_GATE, MCLK, DIV_3);
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break;
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case 4:
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- ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_4);
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+ reg = FIELD_SET(reg, CURRENT_GATE, MCLK, DIV_4);
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break;
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case 6:
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- ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_6);
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+ reg = FIELD_SET(reg, CURRENT_GATE, MCLK, DIV_6);
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break;
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case 8:
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- ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_8);
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+ reg = FIELD_SET(reg, CURRENT_GATE, MCLK, DIV_8);
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break;
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}
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- setCurrentGate(ulReg);
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+ setCurrentGate(reg);
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}
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}
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