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@@ -150,20 +150,6 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
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}
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}
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-static void sdma_v4_0_print_ucode_regs(void *handle)
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-{
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- int i;
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- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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-
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- dev_info(adev->dev, "VEGA10 SDMA ucode registers\n");
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- for (i = 0; i < adev->sdma.num_instances; i++) {
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- dev_info(adev->dev, " SDMA%d_UCODE_ADDR=0x%08X\n",
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- i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR)));
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- dev_info(adev->dev, " SDMA%d_UCODE_CHECKSUM=0x%08X\n",
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- i, RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_CHECKSUM)));
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- }
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-}
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-
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/**
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* sdma_v4_0_init_microcode - load ucode images from disk
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*
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@@ -804,8 +790,6 @@ static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
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WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
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}
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- sdma_v4_0_print_ucode_regs(adev);
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-
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return 0;
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}
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@@ -831,7 +815,6 @@ static int sdma_v4_0_start(struct amdgpu_device *adev)
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}
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if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
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- DRM_INFO("Loading via direct write\n");
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r = sdma_v4_0_load_microcode(adev);
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if (r)
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return r;
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@@ -869,8 +852,6 @@ static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
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u32 tmp;
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u64 gpu_addr;
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- DRM_INFO("In Ring test func\n");
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-
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r = amdgpu_wb_get(adev, &index);
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if (r) {
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dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
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