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@@ -112,6 +112,14 @@
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#define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
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#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
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+#define U3P_U3_PHYD_RXDET1 (SSUSB_SIFSLV_U3PHYD_BASE + 0x128)
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+#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
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+#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
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+
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+#define U3P_U3_PHYD_RXDET2 (SSUSB_SIFSLV_U3PHYD_BASE + 0x12c)
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+#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
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+#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
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+
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#define U3P_XTALCTL3 (SSUSB_SIFSLV_SPLLC + 0x0018)
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#define XC3_RG_U3_XTAL_RX_PWD BIT(9)
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#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
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@@ -295,6 +303,16 @@ static void phy_instance_init(struct mt65xx_u3phy *u3phy,
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tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
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writel(tmp, port_base + U3P_PHYD_CDR1);
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+ tmp = readl(port_base + U3P_U3_PHYD_RXDET1);
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+ tmp &= ~P3D_RG_RXDET_STB2_SET;
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+ tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
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+ writel(tmp, port_base + U3P_U3_PHYD_RXDET1);
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+
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+ tmp = readl(port_base + U3P_U3_PHYD_RXDET2);
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+ tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
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+ tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
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+ writel(tmp, port_base + U3P_U3_PHYD_RXDET2);
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+
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dev_dbg(u3phy->dev, "%s(%d)\n", __func__, index);
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}
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