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@@ -535,9 +535,8 @@ static struct sh_eth_cpu_data r7s72100_data = {
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.rpadir_value = 2 << 16,
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.no_trimd = 1,
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.no_ade = 1,
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- .hw_crc = 1,
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+ .hw_checksum = 1,
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.tsu = 1,
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- .shift_rd0 = 1,
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};
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static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
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@@ -574,10 +573,9 @@ static struct sh_eth_cpu_data r8a7740_data = {
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.rpadir_value = 2 << 16,
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.no_trimd = 1,
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.no_ade = 1,
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- .hw_crc = 1,
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+ .hw_checksum = 1,
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.tsu = 1,
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.select_mii = 1,
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- .shift_rd0 = 1,
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};
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/* There is CPU dependent code */
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@@ -814,9 +812,8 @@ static struct sh_eth_cpu_data sh7734_data = {
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.no_trimd = 1,
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.no_ade = 1,
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.tsu = 1,
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- .hw_crc = 1,
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+ .hw_checksum = 1,
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.select_mii = 1,
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- .shift_rd0 = 1,
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};
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/* SH7763 */
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@@ -931,7 +928,7 @@ static int sh_eth_reset(struct net_device *ndev)
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sh_eth_write(ndev, 0x0, RDFFR);
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/* Reset HW CRC register */
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- if (mdp->cd->hw_crc)
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+ if (mdp->cd->hw_checksum)
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sh_eth_write(ndev, 0x0, CSMR);
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/* Select MII mode */
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@@ -1416,7 +1413,7 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
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* the RFS bits are from bit 25 to bit 16. So, the
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* driver needs right shifting by 16.
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*/
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- if (mdp->cd->shift_rd0)
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+ if (mdp->cd->hw_checksum)
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desc_status >>= 16;
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skb = mdp->rx_skbuff[entry];
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@@ -1990,7 +1987,7 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
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add_reg(MAFCR);
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if (cd->rtrate)
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add_reg(RTRATE);
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- if (cd->hw_crc)
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+ if (cd->hw_checksum)
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add_reg(CSMR);
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if (cd->select_mii)
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add_reg(RMII_MII);
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