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@@ -132,6 +132,15 @@ MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
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/* Goes in read_status_mask for break detection as the HW doesn't do it*/
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/* Goes in read_status_mask for break detection as the HW doesn't do it*/
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#define CDNS_UART_IXR_BRK 0x80000000
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#define CDNS_UART_IXR_BRK 0x80000000
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+/*
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+ * Modem Control register:
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+ * The read/write Modem Control register controls the interface with the modem
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+ * or data set, or a peripheral device emulating a modem.
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+ */
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+#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
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+#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
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+#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
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+
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/*
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/*
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* Channel Status Register:
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* Channel Status Register:
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* The channel status register (CSR) is provided to enable the control logic
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* The channel status register (CSR) is provided to enable the control logic
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@@ -915,7 +924,18 @@ static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
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static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
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static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
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{
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{
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- /* N/A */
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+ u32 val;
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+
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+ val = cdns_uart_readl(CDNS_UART_MODEMCR_OFFSET);
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+
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+ val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
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+
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+ if (mctrl & TIOCM_RTS)
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+ val |= CDNS_UART_MODEMCR_RTS;
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+ if (mctrl & TIOCM_DTR)
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+ val |= CDNS_UART_MODEMCR_DTR;
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+
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+ cdns_uart_writel(val, CDNS_UART_MODEMCR_OFFSET);
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}
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}
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#ifdef CONFIG_CONSOLE_POLL
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#ifdef CONFIG_CONSOLE_POLL
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