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@@ -485,37 +485,14 @@ static int dmar_forcedac;
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static int intel_iommu_strict;
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static int intel_iommu_superpage = 1;
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static int intel_iommu_ecs = 1;
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-static int intel_iommu_pasid28;
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static int iommu_identity_mapping;
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#define IDENTMAP_ALL 1
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#define IDENTMAP_GFX 2
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#define IDENTMAP_AZALIA 4
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-/* Broadwell and Skylake have broken ECS support — normal so-called "second
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- * level" translation of DMA requests-without-PASID doesn't actually happen
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- * unless you also set the NESTE bit in an extended context-entry. Which of
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- * course means that SVM doesn't work because it's trying to do nested
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- * translation of the physical addresses it finds in the process page tables,
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- * through the IOVA->phys mapping found in the "second level" page tables.
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- *
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- * The VT-d specification was retroactively changed to change the definition
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- * of the capability bits and pretend that Broadwell/Skylake never happened...
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- * but unfortunately the wrong bit was changed. It's ECS which is broken, but
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- * for some reason it was the PASID capability bit which was redefined (from
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- * bit 28 on BDW/SKL to bit 40 in future).
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- *
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- * So our test for ECS needs to eschew those implementations which set the old
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- * PASID capabiity bit 28, since those are the ones on which ECS is broken.
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- * Unless we are working around the 'pasid28' limitations, that is, by putting
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- * the device into passthrough mode for normal DMA and thus masking the bug.
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- */
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-#define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap) && \
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- (intel_iommu_pasid28 || !ecap_broken_pasid(iommu->ecap)))
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-/* PASID support is thus enabled if ECS is enabled and *either* of the old
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- * or new capability bits are set. */
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-#define pasid_enabled(iommu) (ecs_enabled(iommu) && \
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- (ecap_pasid(iommu->ecap) || ecap_broken_pasid(iommu->ecap)))
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+#define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap))
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+#define pasid_enabled(iommu) (ecs_enabled(iommu) && ecap_pasid(iommu->ecap))
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int intel_iommu_gfx_mapped;
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EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
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@@ -578,11 +555,6 @@ static int __init intel_iommu_setup(char *str)
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printk(KERN_INFO
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"Intel-IOMMU: disable extended context table support\n");
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intel_iommu_ecs = 0;
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- } else if (!strncmp(str, "pasid28", 7)) {
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- printk(KERN_INFO
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- "Intel-IOMMU: enable pre-production PASID support\n");
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- intel_iommu_pasid28 = 1;
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- iommu_identity_mapping |= IDENTMAP_GFX;
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} else if (!strncmp(str, "tboot_noforce", 13)) {
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printk(KERN_INFO
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"Intel-IOMMU: not forcing on after tboot. This could expose security risk for tboot\n");
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@@ -1606,6 +1578,18 @@ static void iommu_flush_iotlb_psi(struct intel_iommu *iommu,
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iommu_flush_dev_iotlb(domain, addr, mask);
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}
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+/* Notification for newly created mappings */
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+static inline void __mapping_notify_one(struct intel_iommu *iommu,
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+ struct dmar_domain *domain,
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+ unsigned long pfn, unsigned int pages)
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+{
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+ /* It's a non-present to present mapping. Only flush if caching mode */
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+ if (cap_caching_mode(iommu->cap))
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+ iommu_flush_iotlb_psi(iommu, domain, pfn, pages, 0, 1);
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+ else
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+ iommu_flush_write_buffer(iommu);
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+}
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+
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static void iommu_flush_iova(struct iova_domain *iovad)
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{
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struct dmar_domain *domain;
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@@ -2340,18 +2324,47 @@ static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
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return 0;
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}
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+static int domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
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+ struct scatterlist *sg, unsigned long phys_pfn,
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+ unsigned long nr_pages, int prot)
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+{
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+ int ret;
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+ struct intel_iommu *iommu;
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+
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+ /* Do the real mapping first */
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+ ret = __domain_mapping(domain, iov_pfn, sg, phys_pfn, nr_pages, prot);
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+ if (ret)
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+ return ret;
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+
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+ /* Notify about the new mapping */
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+ if (domain_type_is_vm(domain)) {
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+ /* VM typed domains can have more than one IOMMUs */
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+ int iommu_id;
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+ for_each_domain_iommu(iommu_id, domain) {
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+ iommu = g_iommus[iommu_id];
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+ __mapping_notify_one(iommu, domain, iov_pfn, nr_pages);
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+ }
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+ } else {
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+ /* General domains only have one IOMMU */
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+ iommu = domain_get_iommu(domain);
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+ __mapping_notify_one(iommu, domain, iov_pfn, nr_pages);
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+ }
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+
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+ return 0;
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+}
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+
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static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
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struct scatterlist *sg, unsigned long nr_pages,
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int prot)
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{
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- return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
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+ return domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
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}
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static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
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unsigned long phys_pfn, unsigned long nr_pages,
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int prot)
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{
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- return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
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+ return domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
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}
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static void domain_context_clear_one(struct intel_iommu *iommu, u8 bus, u8 devfn)
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@@ -2534,7 +2547,7 @@ static struct dmar_domain *find_or_alloc_domain(struct device *dev, int gaw)
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struct device_domain_info *info = NULL;
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struct dmar_domain *domain = NULL;
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struct intel_iommu *iommu;
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- u16 req_id, dma_alias;
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+ u16 dma_alias;
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unsigned long flags;
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u8 bus, devfn;
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@@ -2542,8 +2555,6 @@ static struct dmar_domain *find_or_alloc_domain(struct device *dev, int gaw)
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if (!iommu)
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return NULL;
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- req_id = ((u16)bus << 8) | devfn;
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-
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if (dev_is_pci(dev)) {
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struct pci_dev *pdev = to_pci_dev(dev);
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@@ -2657,9 +2668,9 @@ static int iommu_domain_identity_map(struct dmar_domain *domain,
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*/
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dma_pte_clear_range(domain, first_vpfn, last_vpfn);
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- return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
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- last_vpfn - first_vpfn + 1,
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- DMA_PTE_READ|DMA_PTE_WRITE);
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+ return __domain_mapping(domain, first_vpfn, NULL,
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+ first_vpfn, last_vpfn - first_vpfn + 1,
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+ DMA_PTE_READ|DMA_PTE_WRITE);
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}
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static int domain_prepare_identity_map(struct device *dev,
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@@ -3626,14 +3637,6 @@ static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr,
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if (ret)
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goto error;
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- /* it's a non-present to present mapping. Only flush if caching mode */
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- if (cap_caching_mode(iommu->cap))
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- iommu_flush_iotlb_psi(iommu, domain,
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- mm_to_dma_pfn(iova_pfn),
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- size, 0, 1);
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- else
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- iommu_flush_write_buffer(iommu);
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-
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start_paddr = (phys_addr_t)iova_pfn << PAGE_SHIFT;
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start_paddr += paddr & ~PAGE_MASK;
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return start_paddr;
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@@ -3820,12 +3823,6 @@ static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nele
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return 0;
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}
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- /* it's a non-present to present mapping. Only flush if caching mode */
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- if (cap_caching_mode(iommu->cap))
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- iommu_flush_iotlb_psi(iommu, domain, start_vpfn, size, 0, 1);
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- else
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- iommu_flush_write_buffer(iommu);
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-
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return nelems;
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}
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Linus Torvalds