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Merge branch 'drm-fixes-4.6' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

Misc radeon and amdgpu bug fixes for 4.6.

* 'drm-fixes-4.6' of git://people.freedesktop.org/~agd5f/linux:
  amdgpu/uvd: add uvd fw version for amdgpu
  drm/amdgpu: forbid mapping of userptr bo through radeon device file
  drm/radeon: forbid mapping of userptr bo through radeon device file
  drm/amdgpu: bump the afmt limit for CZ, ST, Polaris
  drm/amdgpu: use defines for CRTCs and AMFT blocks
  drm/radeon: print a message if ATPX dGPU power control is missing
  Revert "drm/radeon: disable runtime pm on PX laptops without dGPU power control"
  drm/amdgpu/acp: fix resume on CZ systems with AZ audio
  drm/radeon: add a quirk for a XFX R9 270X
  drm/radeon: print pci revision as well as pci ids on driver load
  drm/amdgpu: when suspending, if uvd/vce was running. need to cancel delay work.
  drm/radeon: fix initial connector audio value
Dave Airlie 9 年之前
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18cdfe751f

+ 1 - 0
drivers/gpu/drm/amd/amdgpu/amdgpu.h

@@ -1591,6 +1591,7 @@ struct amdgpu_uvd {
 	struct amdgpu_bo	*vcpu_bo;
 	struct amdgpu_bo	*vcpu_bo;
 	void			*cpu_addr;
 	void			*cpu_addr;
 	uint64_t		gpu_addr;
 	uint64_t		gpu_addr;
+	unsigned		fw_version;
 	void			*saved_bo;
 	void			*saved_bo;
 	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];
 	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];
 	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];
 	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];

+ 4 - 0
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c

@@ -425,6 +425,10 @@ static int acp_resume(void *handle)
 	struct acp_pm_domain *apd;
 	struct acp_pm_domain *apd;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 
+	/* return early if no ACP */
+	if (!adev->acp.acp_genpd)
+		return 0;
+
 	/* SMU block will power on ACP irrespective of ACP runtime status.
 	/* SMU block will power on ACP irrespective of ACP runtime status.
 	 * Power off explicitly based on genpd ACP runtime status so that ACP
 	 * Power off explicitly based on genpd ACP runtime status so that ACP
 	 * hw and ACP-genpd status are in sync.
 	 * hw and ACP-genpd status are in sync.

+ 1 - 1
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

@@ -303,7 +303,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
 			fw_info.feature = adev->vce.fb_version;
 			fw_info.feature = adev->vce.fb_version;
 			break;
 			break;
 		case AMDGPU_INFO_FW_UVD:
 		case AMDGPU_INFO_FW_UVD:
-			fw_info.ver = 0;
+			fw_info.ver = adev->uvd.fw_version;
 			fw_info.feature = 0;
 			fw_info.feature = 0;
 			break;
 			break;
 		case AMDGPU_INFO_FW_GMC:
 		case AMDGPU_INFO_FW_GMC:

+ 3 - 3
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h

@@ -53,7 +53,7 @@ struct amdgpu_hpd;
 
 
 #define AMDGPU_MAX_HPD_PINS 6
 #define AMDGPU_MAX_HPD_PINS 6
 #define AMDGPU_MAX_CRTCS 6
 #define AMDGPU_MAX_CRTCS 6
-#define AMDGPU_MAX_AFMT_BLOCKS 7
+#define AMDGPU_MAX_AFMT_BLOCKS 9
 
 
 enum amdgpu_rmx_type {
 enum amdgpu_rmx_type {
 	RMX_OFF,
 	RMX_OFF,
@@ -309,8 +309,8 @@ struct amdgpu_mode_info {
 	struct atom_context *atom_context;
 	struct atom_context *atom_context;
 	struct card_info *atom_card_info;
 	struct card_info *atom_card_info;
 	bool mode_config_initialized;
 	bool mode_config_initialized;
-	struct amdgpu_crtc *crtcs[6];
-	struct amdgpu_afmt *afmt[7];
+	struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS];
+	struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS];
 	/* DVI-I properties */
 	/* DVI-I properties */
 	struct drm_property *coherent_mode_property;
 	struct drm_property *coherent_mode_property;
 	/* DAC enable load detect */
 	/* DAC enable load detect */

+ 2 - 0
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

@@ -223,6 +223,8 @@ static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 {
 {
 	struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
 	struct amdgpu_bo *rbo = container_of(bo, struct amdgpu_bo, tbo);
 
 
+	if (amdgpu_ttm_tt_get_usermm(bo->ttm))
+		return -EPERM;
 	return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 	return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 }
 }
 
 

+ 5 - 0
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

@@ -158,6 +158,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
 	DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
 	DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n",
 		version_major, version_minor, family_id);
 		version_major, version_minor, family_id);
 
 
+	adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) |
+				(family_id << 8));
+
 	bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
 	bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
 		 +  AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
 		 +  AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE;
 	r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
 	r = amdgpu_bo_create(adev, bo_size, PAGE_SIZE, true,
@@ -255,6 +258,8 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
 	if (i == AMDGPU_MAX_UVD_HANDLES)
 	if (i == AMDGPU_MAX_UVD_HANDLES)
 		return 0;
 		return 0;
 
 
+	cancel_delayed_work_sync(&adev->uvd.idle_work);
+
 	size = amdgpu_bo_size(adev->uvd.vcpu_bo);
 	size = amdgpu_bo_size(adev->uvd.vcpu_bo);
 	ptr = adev->uvd.cpu_addr;
 	ptr = adev->uvd.cpu_addr;
 
 

+ 1 - 0
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c

@@ -234,6 +234,7 @@ int amdgpu_vce_suspend(struct amdgpu_device *adev)
 	if (i == AMDGPU_MAX_VCE_HANDLES)
 	if (i == AMDGPU_MAX_VCE_HANDLES)
 		return 0;
 		return 0;
 
 
+	cancel_delayed_work_sync(&adev->vce.idle_work);
 	/* TODO: suspending running encoding sessions isn't supported */
 	/* TODO: suspending running encoding sessions isn't supported */
 	return -EINVAL;
 	return -EINVAL;
 }
 }

+ 7 - 4
drivers/gpu/drm/radeon/radeon_atpx_handler.c

@@ -62,10 +62,6 @@ bool radeon_has_atpx(void) {
 	return radeon_atpx_priv.atpx_detected;
 	return radeon_atpx_priv.atpx_detected;
 }
 }
 
 
-bool radeon_has_atpx_dgpu_power_cntl(void) {
-	return radeon_atpx_priv.atpx.functions.power_cntl;
-}
-
 /**
 /**
  * radeon_atpx_call - call an ATPX method
  * radeon_atpx_call - call an ATPX method
  *
  *
@@ -145,6 +141,13 @@ static void radeon_atpx_parse_functions(struct radeon_atpx_functions *f, u32 mas
  */
  */
 static int radeon_atpx_validate(struct radeon_atpx *atpx)
 static int radeon_atpx_validate(struct radeon_atpx *atpx)
 {
 {
+	/* make sure required functions are enabled */
+	/* dGPU power control is required */
+	if (atpx->functions.power_cntl == false) {
+		printk("ATPX dGPU power cntl not present, forcing\n");
+		atpx->functions.power_cntl = true;
+	}
+
 	if (atpx->functions.px_params) {
 	if (atpx->functions.px_params) {
 		union acpi_object *info;
 		union acpi_object *info;
 		struct atpx_px_params output;
 		struct atpx_px_params output;

+ 6 - 1
drivers/gpu/drm/radeon/radeon_connectors.c

@@ -2002,10 +2002,12 @@ radeon_add_atom_connector(struct drm_device *dev,
 						   rdev->mode_info.dither_property,
 						   rdev->mode_info.dither_property,
 						   RADEON_FMT_DITHER_DISABLE);
 						   RADEON_FMT_DITHER_DISABLE);
 
 
-			if (radeon_audio != 0)
+			if (radeon_audio != 0) {
 				drm_object_attach_property(&radeon_connector->base.base,
 				drm_object_attach_property(&radeon_connector->base.base,
 							   rdev->mode_info.audio_property,
 							   rdev->mode_info.audio_property,
 							   RADEON_AUDIO_AUTO);
 							   RADEON_AUDIO_AUTO);
+				radeon_connector->audio = RADEON_AUDIO_AUTO;
+			}
 			if (ASIC_IS_DCE5(rdev))
 			if (ASIC_IS_DCE5(rdev))
 				drm_object_attach_property(&radeon_connector->base.base,
 				drm_object_attach_property(&radeon_connector->base.base,
 							   rdev->mode_info.output_csc_property,
 							   rdev->mode_info.output_csc_property,
@@ -2130,6 +2132,7 @@ radeon_add_atom_connector(struct drm_device *dev,
 				drm_object_attach_property(&radeon_connector->base.base,
 				drm_object_attach_property(&radeon_connector->base.base,
 							   rdev->mode_info.audio_property,
 							   rdev->mode_info.audio_property,
 							   RADEON_AUDIO_AUTO);
 							   RADEON_AUDIO_AUTO);
+				radeon_connector->audio = RADEON_AUDIO_AUTO;
 			}
 			}
 			if (connector_type == DRM_MODE_CONNECTOR_DVII) {
 			if (connector_type == DRM_MODE_CONNECTOR_DVII) {
 				radeon_connector->dac_load_detect = true;
 				radeon_connector->dac_load_detect = true;
@@ -2185,6 +2188,7 @@ radeon_add_atom_connector(struct drm_device *dev,
 				drm_object_attach_property(&radeon_connector->base.base,
 				drm_object_attach_property(&radeon_connector->base.base,
 							   rdev->mode_info.audio_property,
 							   rdev->mode_info.audio_property,
 							   RADEON_AUDIO_AUTO);
 							   RADEON_AUDIO_AUTO);
+				radeon_connector->audio = RADEON_AUDIO_AUTO;
 			}
 			}
 			if (ASIC_IS_DCE5(rdev))
 			if (ASIC_IS_DCE5(rdev))
 				drm_object_attach_property(&radeon_connector->base.base,
 				drm_object_attach_property(&radeon_connector->base.base,
@@ -2237,6 +2241,7 @@ radeon_add_atom_connector(struct drm_device *dev,
 				drm_object_attach_property(&radeon_connector->base.base,
 				drm_object_attach_property(&radeon_connector->base.base,
 							   rdev->mode_info.audio_property,
 							   rdev->mode_info.audio_property,
 							   RADEON_AUDIO_AUTO);
 							   RADEON_AUDIO_AUTO);
+				radeon_connector->audio = RADEON_AUDIO_AUTO;
 			}
 			}
 			if (ASIC_IS_DCE5(rdev))
 			if (ASIC_IS_DCE5(rdev))
 				drm_object_attach_property(&radeon_connector->base.base,
 				drm_object_attach_property(&radeon_connector->base.base,

+ 4 - 10
drivers/gpu/drm/radeon/radeon_device.c

@@ -103,12 +103,6 @@ static const char radeon_family_name[][16] = {
 	"LAST",
 	"LAST",
 };
 };
 
 
-#if defined(CONFIG_VGA_SWITCHEROO)
-bool radeon_has_atpx_dgpu_power_cntl(void);
-#else
-static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
-#endif
-
 #define RADEON_PX_QUIRK_DISABLE_PX  (1 << 0)
 #define RADEON_PX_QUIRK_DISABLE_PX  (1 << 0)
 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
 #define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
 
 
@@ -1305,9 +1299,9 @@ int radeon_device_init(struct radeon_device *rdev,
 	}
 	}
 	rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS);
 	rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS);
 
 
-	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
-		radeon_family_name[rdev->family], pdev->vendor, pdev->device,
-		pdev->subsystem_vendor, pdev->subsystem_device);
+	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
+		 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
+		 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
 
 
 	/* mutex initialization are all done here so we
 	/* mutex initialization are all done here so we
 	 * can recall function without having locking issues */
 	 * can recall function without having locking issues */
@@ -1439,7 +1433,7 @@ int radeon_device_init(struct radeon_device *rdev,
 	 * ignore it */
 	 * ignore it */
 	vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
 	vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
 
 
-	if ((rdev->flags & RADEON_IS_PX) && radeon_has_atpx_dgpu_power_cntl())
+	if (rdev->flags & RADEON_IS_PX)
 		runtime = true;
 		runtime = true;
 	vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
 	vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
 	if (runtime)
 	if (runtime)

+ 2 - 0
drivers/gpu/drm/radeon/radeon_ttm.c

@@ -235,6 +235,8 @@ static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 {
 {
 	struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
 	struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
 
 
+	if (radeon_ttm_tt_has_userptr(bo->ttm))
+		return -EPERM;
 	return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 	return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp);
 }
 }
 
 

+ 1 - 0
drivers/gpu/drm/radeon/si_dpm.c

@@ -2931,6 +2931,7 @@ static struct si_dpm_quirk si_dpm_quirk_list[] = {
 	{ PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
 	{ PCI_VENDOR_ID_ATI, 0x6811, 0x1462, 0x2015, 0, 120000 },
 	{ PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
 	{ PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 },
 	{ PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
 	{ PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 },
+	{ PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 },
 	{ 0, 0, 0, 0 },
 	{ 0, 0, 0, 0 },
 };
 };