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@@ -1326,6 +1326,21 @@ static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
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writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
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}
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+static void at91_gpio_set_multiple(struct gpio_chip *chip,
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+ unsigned long *mask, unsigned long *bits)
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+{
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+ struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
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+ void __iomem *pio = at91_gpio->regbase;
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+
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+#define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
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+ /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */
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+ uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio);
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+ uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio);
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+
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+ writel_relaxed(set_mask, pio + PIO_SODR);
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+ writel_relaxed(clear_mask, pio + PIO_CODR);
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+}
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+
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static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
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int val)
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{
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@@ -1685,6 +1700,7 @@ static struct gpio_chip at91_gpio_template = {
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.get = at91_gpio_get,
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.direction_output = at91_gpio_direction_output,
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.set = at91_gpio_set,
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+ .set_multiple = at91_gpio_set_multiple,
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.dbg_show = at91_gpio_dbg_show,
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.can_sleep = false,
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.ngpio = MAX_NB_GPIO_PER_BANK,
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